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d a t a sh eet preliminary speci?ation file under integrated circuits, ic28 2000 jul 26 integrated circuits P8XC591 single-chip 8-bit microcontroller with can controller
2000 jul 26 2 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 contents 1 features 1.1 80c51 related features of the 8xc591 1.2 can related features of the 8xc591 2 general description 3 ordering information 4 block diagram 5 functional diagram 6 pinning information 6.1 pinning diagram 6.2 pin description 7 memory organization 7.1 program memory 7.2 addressing 7.3 expanded data ram addressing 7.4 dual dptr 8 i/o facilities 9 oscillator characteristics 10 reset 11 low power modes 11.1 stop clock mode 11.2 idle mode 11.3 power-down mode 12 can, controller area network 12.1 features of the pelican controller 12.2 pelican structure 12.3 communication between pelican controller and cpu 12.4 register and message buffer description 12.5 can registers 13 serial i/o 14 sio0 standard serial interface uart 14.1 multiprocessor communications 14.2 serial port control register 14.3 baud rate generation 14.4 more about uart modes 14.5 enhanced uart 15 sio1, i 2 c serial io 15.1 modes of operation 15.2 sio1 implementation and operation 15.3 software examples of sio1 service routines 16 timer 2 16.1 features of timer 2 17 watchdog timer (t3) 18 pulse width modulated outputs 18.1 prescaler frequency control register (pwmp) 18.2 pulse width register 0 (pwm0) 18.3 pulse width register 1 (pwm1) 19 port 1 operation 20 analog-to-digital converter (adc) 20.1 adc features 20.2 adc functional description 20.3 10-bit analog-to-digital conversion 20.4 10-bit adc resolution and analog supply 20.5 power reduction modes 21 interrupts 21.1 interrupt enable registers 21.2 interrupt enable and priority registers 21.3 interrupt priority 21.4 interrupt vectors 22 instruction set 22.1 addressing modes 23 limiting values 24 dc characteristics 25 ac characteristics 25.1 timing symbol definitions 26 eprom characteristics 26.1 program verification 26.2 security bits 27 package outlines 28 soldering 28.1 plastic leaded-chip carriers/quad flat-packs 29 definitions 30 life support applications
2000 jul 26 3 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 1 features 1.1 80c51 related features of the 8xc591 ? full static 80c51 central processing unit available as otp, rom and romless ? 16 kbytes internal program memory expandable externally to 64 kbytes ? 512 bytes on-chip data ram expandable externally to 64 kbytes ? three 16-bit timers/counters t0, t1 (standard 80c51) and additional t2 (capture & compare) ? 10-bit adc with 6 multiplexed analog inputs with fast 8-bit adc option ? two 8-bit resolution, pulse width modulated outputs ? 32 i/o port pins in the standard 80c51 pinout ? i 2 c-bus serial i/o port with byte oriented master and slave functions ? on-chip watchdog timer t3 ? extended temperature range: ? 40 to +85 c ? accelerated (prescaler 1:1) instruction cycle time 500 ns @ 12 mhz ? operation voltage range: 5 v 5% ? security bits: rom version has 2 bits otp/eprom version has 3 bits ? 32 bytes encryption array ? 4 level priority interrupt, 15 interrupt sources ? full-duplex enhanced uart with programmable baudrate generator ? power control modes: clock can be stopped and resumed idle mode power-down mode ? adc active in idle mode ? second dptr register ? ale inhibit for emi reduction ? programmable i/o port pins (pseudo bi-directional, push-pull, high impedance, open drain) ? wake-up from power-down by external interrupts ? software reset bit (auxr1.5) ? low active reset pin ? power-on detect reset ? once mode 1.2 can related features of the 8xc591 ? can 2.0b active controller, supporting 11-bit standard and 29-bit extended indentifiers ? 1 mbit/s can bus speed with 8 mhz clock achievable ? 64 byte receive fifo (can capture sequential data frames from the same source as required by the transport layer of higher protocols such as devicenet, canopen and osek) ? 13 byte transmit buffer ? enhanced pelican core (from the sja1000 stand-alone can2.0b controller) 1.2.1 p eli can f eatures ? four independently configurable screeners (acceptance filters) ? each screener has two 32-bit specifies: 32-bit match and 32-bit mask ? 32-bits of mask per screener allows unique group addressing per screener ? higher layer protocols especially supported in standard can format with: up to four, 11-bit id screeners that also screen the two (2) data bytes i.e., data frames are screened by the can id and by data byte content ? up to eight, 11-bit id screeners half of which also screen the first data byte ? all screeners are changeable ?n the fly ? listen only mode, self test mode ? error code capture, arbitration lost capture, readable error counters
2000 jul 26 4 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 2 general description the P8XC591 is a single-chip 8-bit-high-performance microcontroller, with on-chip can-controller, derived from the 80c51 microcontroller family. it uses the powerful 80c51 instruction set and includes the successful pelican functionality of the sja1000 can controller from philips semiconductors. the fully static core provides extended power save provisions as the oscillator can be stopped and easily restarted without loss of data. the improved internal clock prescaler of 1:1 achieves a 500 ns instruction cycle time at 12 mhz external clock rate. figure 1 shows a block diagram of the P8XC591. the microcontroller is manufactured in an advanced cmos process, and is designed for use in automotive and general industrial applications. in addition to the 80c51 standard features, the device provides a number of dedicated hardware functions for these applications. two versions of the P8XC591 will be offered: ? p83c591 (with rom) ? p87c591 (with otp) hereafter these versions will be referred to as P8XC591. the temperature range includes (max. f clk = 12 mhz): ? -40 to +85 c version, for general applications the P8XC591 combines the functions of the p87c554 (microcontroller) and the sja1000 (stand-alone can-controller) with the following enhanced features: ? enhanced can receive interrupt (level sensitive) ? extended acceptance filter ? acceptance filter changeable ?n the fly? the main differences between P8XC591 and p87c554 are: ? can-controller on chip ? 6-input adc ? low active reset ? 44 leads. 3 ordering information type number package temperature range ( c) name description version p83c591vfa plcc44 plastic leaded chip carrier; 44 leads sot187-2 ? 40 to +85 p87c591vfa p83c591vfb qfp44 plastic quad ?t package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 p87c591vfb
2000 jul 26 5 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 4 block diagram fig.1 block diagram P8XC591. handbook, full pagewidth mhi001 16-bit timer/event counter with capture (t2) parallel i/o ports watchdog timer (t3) two 16-bit timer/event counters (t0/t1) 16 kbytes program memory 512 bytes data memory cpu core oscillator i 2 c serial interface cpu interface (sfrs) txdc scl sda rt2 t2 p3 p2 p1 p0 rst a0 to a7 v dd v ss xtal2 xtal1 cmsr0 to 5 cmt0 to 1 ct0x/intx rxdc uart rxd txd can 2.0 b interface pwm pwm0 an0 to 5 av ref + av ss ea pwm1 adc P8XC591 t1 t0 80c51 configurable core int1 int0 rd wr psen ale
2000 jul 26 6 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 5 functional diagram fig.2 functional diagram. handbook, full pagewidth mhi002 P8XC591 (44-pin) 0 1 2 3 4 5 6 7 port 0 v dd v ss 0 1 2 3 4 5 6 7 port 1 0 1 2 3 4 5 6 7 port 2 address bus ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 and data bus low order address alternative functions rxdc can i 2 c txdc adc0 adc1 adc2 adc3 ct0i/int2 ct1i/int3 ct2i/int4 ct3i/int5 adc4 adc5 scl sda 0 1 2 3 4 5 6 7 port 3 rxd txd int0 int1 t0 t1 t2 rt2 csmr0 csmr1 csmr2 csmr3 wr rd av ref + av ss pwm1 pwm0 ea ale xtal1 xtal2 psen rst
2000 jul 26 7 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 6 pinning information 6.1 pinning diagram fig.3 pinning diagram for 44-lead lcc package. handbook, full pagewidth P8XC591 mhi003 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 p1.4/adc2/int4/ct2i p1.3/adc1/int3/ct1i p1.2/adc0/int2/ct0i p1.1/txdc p1.0/rxdc av ss av ref + p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p3.6/wr p3.7/rd xtal2 xtal1 v ss v dd p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 ct3i/int5/adc3/p1.5 scl/adc4/p1.6 sda/adc5/p1.7 rst t2/p3.0/rxd pwm0 rt2/p3.1/txd cmsr0/p3.2/int0 cmsr1/p3.3/int1 cmsr2/p3.4/t0 cmsr3/p3.5/t1 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/v pp pwm1 ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13
2000 jul 26 8 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.4 pinning diagram for 44-lead plastic quad flat package (qfp). handbook, full pagewidth P8XC591 mhi004 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 p1.4/adc2/int4/ct2i p1.3/adc1/int3/ct1i p1.2/adc0/int2/ct0i p1.1/txdc p1.0/rxdc av ss av ref + p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p3.6/wr p3.7/rd xtal2 xtal1 v ss v dd p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5/adc3/int5/ct3i p1.6/adc4/scl p1.7/adc5/sda rst p3.0/t2/rxd pwm0 rt2/p3.1/txd cmsr0/p3.2/int0 cmsr2/p3.4/t0 cmsr3/p3.5/t1 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/v pp pwm1 ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 cmsr1/p3.3/int1
2000 jul 26 9 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 6.2 pin description table 1 pin description for qfp44/plcc44, see note 1. symbol pin description qfp44 plcc44 rst 4 10 reset: a input to reset the P8XC591. it also provides a reset pulse as output when timer t3 over?ws. p3.0to p3.7 port 3 (p3.0 to p3.7) : 8-bit programmable i/o port lines; port 3 can sink/source 4 lsttl inputs. port 3 pins serve alternate functions as follows: p3.0/rxd 5 11 rxd : serial input port for uart; t2: t2 event input p3.1/txd 7 13 txd : serial output port for uart; rt2: t2 timer reset signal. rising edge triggered. p3.2/ int0/cmsr0 8 14 int0 : external interrupt input 0; cmsr0: compare and set/reset output for timer t2. p3.3/ int1/ cmsr1 915 int1 : external interrupt input 1; cmsr1: compare and set/reset output for timer t2. p3.4/t0/cmsr2 10 16 t0 : timer 0 external interrupt input; cmsr2: compare and set/reset output for timer t2. p3.5/t1/cmsr3 11 17 t1 : timer 1 external interrupt input; cmsr3: compare and set/reset output for timer t2. p3.6/ wr 12 18 wr : external data memory write strobe; p3.7/ rd 13 19 rd : external data memory read strobe. during reset, port 3 will be asynchronously driven resistive high. port 3 has four modes selected on a per bit basis by writing to the p3m1 and p3m2 registers as follows: p3m1.x 0 0 1 1 p3m2.x 0 1 0 1 mode description pseudo-bidirectional (standard c51 con?uration default) push-pull high impedance open drain xtal2 14 20 crystal pin 2: output of the inverting ampli?r that forms the oscillator. left open-circuit when an external oscillator clock is used. xtal1 15 21 crystal pin 1: input to the inverting ampli?r that forms the oscillator, and input to the internal clock generator. receives the external oscillator clock signal when an external oscillator is used. v ss 16 22 ground; circuit ground potential. v dd 17 23 power supply; power supply pin during normal operation and power reduction modes.
2000 jul 26 10 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 p2.0/a08 to p2.7/a15 18 to 25 24 to 31 port 2 (p2.0 to p2.7) : 8-bit programmable i/o port lines; a08 to a15 : high-order address byte for external memory. alternate function: high-order address byte for external memory (a08-a15). port 2 is also used to input the upper order address during eprom programming and veri?ation. a8 is on p2.0, a9 on p2.1, through a12 on p2.4. during reset, port 2 will be asynchronously driven high. port 2 has four output modes selected on a per bit basis by writing to the p2m1 and p2m2 registers as follows: p2m1.x 0 0 1 1 p2m2.x 0 1 0 1 mode description pseudo-bidirectional (standard c51 con?uration default) push-pull high impedance open drain psen 26 32 program store enable output: read strobe to the external program memory via ports 0 and 2. is activated twice each machine cycle during fetches from external program memory. when executing out of external program memory two activations of psen are skipped during each access to external data memory. psen is not activated (remains high) during no fetches from external program memory. psen can sink/source 8 lsttl inputs. it can drive cmos inputs without external pull-ups. ale/ pr og 27 33 address latch enable output. latches the low byte of the address during access of external memory in normal operation. it is activated every six oscillator periods except during an external data memory access. ale can sink/source 8 lsttl inputs. it can drive cmos inputs without an external pull-up. to prohibit the toggling of ale pin (rfi noise reduction) the bit a0 (sfr: auxr.0) must be set by software; see table 4. pr og : the programming pulse input; alternative function for the p87c591. ea/v pp 29 35 external access input. if, during reset, ea is held at a ttl level high the cpu executes out of the internal program memory. if, during reset, ea is held at a ttl level low the cpu executes out of external program memory via port 0 and port 2. ea is not allowed to ?at. ea is latched during reset and don? care after reset. v pp : the programming supply voltage; alternative function for the p87c591. p0.0/ad0 to p0.7/ad7 30 to 37 36 to 43 port 0 : 8-bit open-drain bidirectional i/o port. during reset, port 0 is high-impedance (tri-state). ad7 to ad0 : multiplexed low-order address and data bus for external memory. during these accesses internal pull-ups are activated. port 0 can sink/source up to 8 lsttl inputs. av ref+ 38 44 analog to digital conversion reference resistor: high-end. av ss 39 1 analog ground. symbol pin description qfp44 plcc44
2000 jul 26 11 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 notes 1. to avoid ?atch-up effect as power-on, the voltage on any pin at any time must not be higher or lower than v dd + 0.5 v or v ss ? 0.5 v. 2. not implemented for p1.6 and p1.7. p1.0 to p1.4 p1.5 to p1.7 40 to 44 1to3 2to6 7to9 port 1: 8-bit i/o port with a user con?urable output type. the operation of port 1 pins as inputs or outputs depends upon the port con?uration selected. each port pin is con?ured independently. port 1 also provides various special functions as described below: p1.0 40 2 rxdc: can receiver input line. p1.1 41 3 txdc: can transmit output line. during reset, port p1.0 and p1.1 will be asynchronously driven resistive high, p1.2 to p1.7 is high-impedance (tri-state). p1.2 to p1.4 42 to 44 4 to 6 ct0i/int2 / ct1i/int3 / ct2i/int4: t2 capture timer inputs or external interrupt inputs. p1.5 to p1.7 1 to 3 7 to 9 adc0 to adc2: alternate function: input channels to adc. adc3 to adc5: input channels to adc: p1.5 1 7 ct3i/int5: t2 capture timer input or external interrupt inputs. p1.6 2 8 scl: serial port clock line i 2 c. push-pull or pseudo bidrectional modes is not implemented at i 2 c. p1.7 3 9 sda: serial data clock line i 2 c.push-pull or pseudo bidrectional modes is not implemented at i 2 c. port 1 has four modes selected on a per bit basis by writing to the p1m1 and p1m2 registers as follows: p1m1.x 0 0 1 1 p1m2.x 0 1 0 1 mode description pseudo-bidirectional (standard c51 con?uration default (2) ) push-pull (2) high impedance open drain port 1 is also used to input the lower order address byte during eprom programming and veri?ation. a0 is on p1.0, etc. pwm0 6 12 pulse width modulation: output 0. pwm1 28 34 pulse width modulation: output 1. symbol pin description qfp44 plcc44
2000 jul 26 12 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 7 memory organization the central processing unit (cpu) manipulates operands in three memory spaces as follows (see fig.5): ? 16 kbytes internal resp. 64 kbytes external program memory ? 512 bytes internal data memory main-and auxiliary ram ? up to 64 kbytes external data memory (with 256 bytes residing in the internal auxiliary ram). fig.5 memory map and address space with extram = 0. handbook, full pagewidth mhi005 indirect only direct and indirect auxiliary ram (extram = 0) sfrs 255 127 0 external (ea = 0) internal (ea = 1) main ram internal data memory external data memory program memory external 64k 64k 16384 16383 0 overlapped space 256
2000 jul 26 13 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 7.1 program memory the P8XC591 contains 16 kbytes of on-chip program memory which can be extended to 64 kbytes with external memories. when ea pin is held high, the P8XC591 fetches instructions from internal rom unless the address exceeds 3fffh. locations 4000h to ffffh are fetched from external program memory. when the ea pin is held low, all instruction fetches are from external memory. the ea pin is latched during reset and is ?on? care after reset. both, for the rom and eprom version of the P8XC591, precautions are implemented to protect the device against illegal program memory code reading. 7.2 addressing the P8XC591 has five methods for addressing the program and data memory: ? register ? direct ? register-indirect ? immediate ? base-register plus index-register-indirect. for more details about addressing modes please refer to section 22.1 ?ddressing modes? 7.3 expanded data ram addressing the P8XC591 has internal data memory that is mapped into four separate segments: the lower 128 bytes of ram, upper 128 bytes of ram, 128 bytes special function register (sfr), and 256 bytes auxiliary ram (aux-ram) as shown in figure 5. the four segments are: 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable (see fig.6). 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable. 3. the special function registers, sfrs, (addresses 80h to ffh) are directly addressable only. all these sfrs are described in table 4. 4. the 256-bytes aux-ram (00h - ffh) are indirectly accessed by move external instruction, movx, and within the extram bit cleared, see table 3. the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically separate from sfr space. when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. instructions that use direct addressing access sfr space. for example: mov 0a0h,#data accesses the sfr at location 0a0h (which is p2). instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @ r0,#data where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). the aux-ram can be accessed by indirect addressing, with extram bit cleared and movx instructions. this part of memory is physically located on-chip, logically occupies the first 256-bytes of external data memory. with extram = 0, the aux-ram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to aux-ram will not affect ports p0, p3.6 (wr#) and p3.7 (rd#). p2 sfr is output during external addressing. for example, with extram = 0, mov @ r0,#data where r0 contains 0a0h, access the aux-ram at address 0a0h rather than external memory. an access to external data memory locations higher than ffh (i.e., 0100h to ffffh) will be performed with the movx dptr instructions in the same way as in the standard 80c51, so with p0 and p2 as data/address bus, and p3.6 and p3.7 as write and read timing signals. refer to table 4. with extram = 1, movx @ ri and movx @ dptr will be similar to the standard 80c51. movx @ ri will provide an 8-bit address multiplexed with data on port 0 and any output port pins can be used to output higher order address bits. this is to provide the external paging capability. movx @ dptr will generate a 16-bit address. port 2 outputs the high-order eight address bits (the contents of dph) while port 0 multiplexes the low-order eight address bits (dpl) with data. movx @ ri and movx @ dptr will generate either read or write signals on p3.6 (#wr) and p3.7 (#rd). the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack cannot be located in the aux-ram.
2000 jul 26 14 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 2 aux-ram page register (address 8eh) table 3 description of aux-ram bits notes 1. user software should not write ?? to reserved bits. these bits may be used in future 80c51 family products to invoke new features. in that case, the reset or inactive of the new bit will be 0, and its active value will be ?? the value read from a reserved bit is indeterminate. 2. reset value is ?xxxxx10b? 76543210 - - - - - lvadc extram ao bit symbol function 7 to 3 ? reserved for future use; see note 1. 2 lvadc enable a/d low voltage operation. lvadc 0 1 operating mode turns off a/d charge pump. turns on a/d charge pump. required for operation below 4 v. 1 extram internal/external ram (00h - ffh) access using movx @ ri / @ dptr extram 0 1 operating mode internal aux-ram (00h - fh) access using movx @ ri / @ dptr. external data memory access. 0 ao disable/enable ale. ao 0 1 operating mode ale is permitted at a constant rate of 1/6 the oscillator frequency. ale is active only during a movx or movc instruction.
2000 jul 26 15 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.6 internal main ram bit addresses. handbook, full pagewidth mhi006 7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60 5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50 4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 18h 17h 10h 0fh 08h 07h 00h 24 23 31 16 15 8 7 0 register bank 3 register bank 2 register bank 1 register bank 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 (msb) (lsb) 127 7fh 2fh 2eh 2dh 2ch 2bh 2ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1fh
2000 jul 26 16 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 7.3.1 s pecial f unction r egisters table 4 special function register bit address, symbol or alternate port function * = sfrs are bit addressable; # = sfrs are modi?d from or added to the 80c51 sfrs. name description sfr addr bit functions and addresses reset value msb lsb acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h adch# a/d converter high c6h xxxxxxxxb adcon# a/d control c5h adc.1 adc.0 - adci adcs aadr2 aadr1 aadr0 xx000000b auxr auxiliary 8eh - - - - - lvadc extram a0 xxxxx110b auxr1 auxiliary a2h adc8 aidl srst wde wupd 0 - dps 000000x0b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ctcon# capture control ebh ctn3 ctp3 ctn2 ctp2 ctn1 ctp1 ctn0 ctp0 00h cth3# capture high 3 cfh xxxxxxxxb cth2# capture high 2 ceh xxxxxxxxb cth1# capture high 1 cdh xxxxxxxxb cth0# capture high 0 cch xxxxxxxxb cmh2# compare high 2 cbh 00h cmh1# compare high 1 cah 00h cmh0# compare high 0 c9h 00h ctl3# capture low 3 afh xxxxxxxxb ctl2# capture low 2 aeh xxxxxxxxb ctl1# capture low 1 adh xxxxxxxxb ctl0# capture low 0 ach xxxxxxxxb cml2# compare low 2 abh 00h cml1# compare low 1 aah 00h cml0# compare low 0 a9h 00h dptr: data pointer (2 bytes): dph data pointer high 83h 00h dpl data pointer low 82h 00h af ae ad ac ab aa a9 a8 ieno*# interrupt enable 0 a8h ea ead es1 es0 et1 ex1 et0 ex0 00h ef ee ed ec eb ea e9 e8 ien1*# interrupt enable 1 e8h et2 ecan ecm1 ecm0 ect3 ect2 ect1 ect0 00h bf be bd bc bb ba b9 b8 ip0*# interrupt priority 0 b8h - pad ps1 ps0 pt1 px1 pt0 px0 x0000000b ff fe fd fc fb fa f9 f8 ip0h interrupt priority 0 high b7h - padh ps1h ps0h pt1h px1h pt0h px0h x0000000b ip1*# interrupt priority 1 f8h pt2 pcan pcm1 pcm0 pct3 pct2 pct1 pct0 00h ip1h interrupt priority 1 high f7h pt2h pcanh pcm1h pcm0h pct3h pct2h pct1h pct0h 00h canmod can mode register c4h 00h cancon can command (w) and interrupt (r) c3h 00h candat can data c2h 00h canadr can address c1h 00h c7 c6 c5 c4 c3 c2 c1 c0 cansta* can status (r) c0h bs es ts rs tcs tbs dos rbs 00h can interrupt enable (w) beie alie epie wuie doie eie tie rie
2000 jul 26 17 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 p1m1 port 1 output mode 1 92h fch p1m2 port 1 output mode 2 93h 00h p2m1 port 2 output mode 1 94h 00h p2m2 port 2 output mode 2 95h 00h p3m1 port 3 output mode 1 9ah 00h p3m2 port 3 output mode 2 9bh 00h b7 b6 b5 b4 b3 b2 b1 b0 - - csmr3 csmr2 csmr1 csmr0 rt2 t2 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h a15 a14 a13 a12 a11 a10 a9 a8 ffh 97 96 95 94 93 92 91 90 adc5 adc4 adc3 adc2 adc1 adc0 ?? p1* port 1 90h sda scl ct3i ct2i ct1i ct0i txdc rxdc ffh 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh pcon power control 87h smod1 smod0 pof wle gf1 gf0 pd idl 00x00000b psw program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h pwmp# pwm prescaler feh 00h pwmp1# pwm register 1 fdh 00h pwmp0# pwm register 0 fch 00h rte# reset enable efh rp35 rp34 rp33 rp32 xxxx0000b s0addr serial 0 slave address f9h 00h s0aden slave address mask b9h 00h sp stack pointer 81h 07h s0buf serial 0 data buffer 99h xxxxxxxxb s0psl prescaler value uart fah 00h s0psh prescaler/value uart fbh sps prescaler higher nibble 0xxx0000b 9f 9e 9d 9c 9b 9a 99 98 s0con* serial 0 control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h s1con#* serial 1control d8h cr2 ens1 sta st0 si aa cr1 cr0 00h s1adr# serial 1 address dbh slave address gc 00h s1dat# serial 1 data dah 00h s1sta# serial 1 status d9h sc4 sc3 sc2 sc1 sc0 0 0 0 f8h df de dd dc db da d9 d8 ste# set enable eeh sp35 sp34 sp33 sp32 xxxx0000b th1 timer high 1 8dh 00h th0 timer high 0 8ch 00h tl1 timer low 1 8bh 00h tl0 timer low 0 8ah 00h tmh2# timer high 2 edh 00h tml2# timer low 2 ech 00h name description sfr addr bit functions and addresses reset value msb lsb
2000 jul 26 18 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tm2con# timer 2 control eah t2is1 t2is0 t2er t2b0 t2p1 t2p0 t2ms1 t2ms0 00h cf ce cd cc cb ca c9 c8 tm2ir#* timer 2/can int flag reg c8h t2ov cmi2/ can cmi1 cmi0 cti3 cti2 cti1 cti0 00h t3# timer 3 ffh 00h name description sfr addr bit functions and addresses reset value msb lsb
2000 jul 26 19 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.7 dual dptr: handbook, full pagewidth dph (83h) bt0 auxr1 dps dpl (82h) external data memory dptr0 mhi007 dptr1 7.4 dual dptr the dual dptr structure (see figure 7) is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 that allows the program code to switch between them. the dps bit status should be saved by software when switching between dptr0 and dptr1. note that bit 2 is not writable and is always read as a zero. this allows the dps bit to be quickly toggled simply by executing an inc auxr1 instruction without affecting the other bits. dptr instructions the instructions that refer to dptr refer to the data pointer that is currently selected using the auxr1/bit 0 register. the six instructions that use the dptr are as follows: inc dptrincrements the data pointer by 1 mcv dptr, #data 16 loads the dptr with a 16-bit constant mov a, @ a+dptr move code byte relative to dptr to acc movx a, @ dptr move external ram (16-bit address) to acc movx @ dptr, a move acc to external ram (16-bit address) jmp @ a + dptr jump indirect relative to dptr the data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the sfrs. see application note an458 for more details.
2000 jul 26 20 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 7.4.1 auxr1 p age r egister table 5 auxr1 page register (address a2h) table 6 description of auxr1 of bits user software should not write 1s to reserved bits. theses bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. the value read from a reserved bit is indeterminate. the reset value of auxr1 is (000000xb). 76543210 adc8 aidl srst wde wupd 0 ? dsp bit symbol description 7 adc8 adc mode switch . switches between 10-bit conversion and 8-bit conversion adc8 0 1 operating mode 10-bit conversion (50 machine cycles) 8-bit conversion (24 machine cycles) 6 aidl enables the adc during idle mode. 5 srst software reset. 4 wde watchdog timer enable flag . 3 wupd enable wake-up from power-down . 20 reserved. 1 ? reserved. 0 dsp data pointer switch . switches between dprt0 and dptr1. adc8 0 1 operating mode dptr0 dptr1
2000 jul 26 21 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 8 i/o facilities the P8XC591 consists of 32 i/o port lines with partly multiple functions. the i/o? are held high during reset (asynchronous, before oscillator is running). ports 0, 1, 2 and 3 perform the following alternative functions: port 0 is the same as in the 80c51. after reset the port special function register is set to ?fh as known from other 80c51 derivatives. port 0 also provides the multiplexed low-order address and data bus used for expanding the P8XC591 with standard memories and peripherals. port 1 supports several alternative functionalities. for this reason it has different i/o stages. note, port p1.0 and p1.1 are driven-high and p1.2 to p1.7 are high-impedance (tri-state) after reset. port 2 is the same as in the 80c51. after reset the port special function register is set to ?fh as known from other 80c51 derivatives. port 2 also provides the high-order address bus when the P8XC591 is expanded with external program memory and/or external data memory. port 3 is the same as in the 80c51. during reset the port 3 special function register is set to ?fh as known from other 80c51 derivatives. 9 oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal. however, minimum and maximum high and low times specified in the data sheet must be observed. 10 reset a reset is accomplished by holding the rst pin low for at least two machine cycles (12 oscillator periods), while the oscillator is running. to insure a good power-on reset, the rst pin must be low long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. the rst line can also be pulled low internally by a pull-down transistor activated by the watchdog timer t3. the length of the output pulse from t3 is 3 machine cycles. a pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible. note that the short reset pulse from timer t3 cannot discharge the power-on reset capacitor (see figure 8). consequently, when the watchdog timer is also used to set external devices, this capacitor arrangement should not be connected to the rst pin, and a different circuit should be used to perform the power-on reset operation. a timer t3 overflow, if enabled, will force a reset condition to the P8XC591 by an internal connection, whether the output rst is pulled-up high or not. a reset may be performed in software by setting the software reset bit, srst (auxr1.5). this device also has a power-on detect reset circuit as v cc transitions from v cc past v rst . fig.8 on-chip reset configuration. handbook, halfpage mhi008 schmitt trigger reset circuitry rst overflow timer t3 on-chip resistor v dd fig.9 power-on reset. handbook, halfpage mhi009 rst r rst 2.2 f P8XC591 v dd
2000 jul 26 22 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 11 low power modes 11.1 stop clock mode the static design enables the clock speed to be reduced down to 0 mhz (stopped). when the oscillator is stopped, the ram and special function registers retain their values. this mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. for lowest power consumption the power-down mode is suggested. 11.2 idle mode in the idle mode (see table 7), the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. 11.3 power-down mode to save even more power, a power-down mode (see table 7) can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their values down to 2.0 v and care must be taken to return v cc to the minimum specified operating voltages before the power-down mode is terminated. a hardware reset or external interrupt can be used to exit from power-down. the wake-up from power-down bit, wupd (auxr1.3) must be set in order for an interrupt to cause a wake-up from power-down. reset redefines all the sfrs but does not change the on-chip ram. a wake-up allows both the sfrs and the on-chip ram to retain their values. to properly terminate power-down the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). table 7 status of external pins during idle and power-down modes with an external interrupt, int0 and int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power-down. mode memory ale psen port 0 port 1 port 2 port 3 pwm0/ pwm1 idle internal 1 1 port data port data port data port data high external 1 1 ?at port data address port data high power-down internal 0 0 port data port data port data port data high external 0 0 ?at port data port data port data high
2000 jul 26 23 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 11.3.1 p ower o ff f lag the power off flag (pof) is set by on-chip circuitry when the v cc level on the P8XC591 rises from 0 to 5 v. the pof bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or warm after power-down. the v cc level must remain above 3 v for the pof to remain unaffected by the v cc level. 11.3.2 d esign c onsideration ? when the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. 11.3.3 once tm m ode the once tm (?n-circuit emulation? mode facilities testing and debugging of systems without the device having to be removed from the circuit. the once mode is invoked by: 1. pull ale low while the device is in reset an psen is high, 2. hold ale low as rst is deactivated. while the device is in once mode, the port 0 pins go into a float state, and the other port pins and ale and psen are weakly pulled high. the oscillator circuit remains active. while the device is in this mode, an emulator or test cpu can be used to drive the circuit. normal operation is restored when a normal reset is applied. 11.3.4 r educed emi m ode the ale-off bit, ao (auxr.0) can be set to 0 disable the ale output. it will automatically become active when required for external memory accesses and resume to the off state after completing the external memory access. 11.3.5 p ower c ontrol r egister (pcon) table 8 power control register (address 87h) table 9 description of pcon bits if logic 1s are written to pd and idl at the same time, pd takes precedence. the reset value of pcon is (0xx00000). 76543210 smod1 smod0 pof wle gf1 gf0 pd idl bit symbol description 7 smod1 double baud rate . when set to logic 1 the baud rate is doubled when the serial port sio0 is being used in modes 1, 2 and 3. 6 smod0 double baud rate. selects sm0/fe for scon.7 bit. 5 pof power off ?g . 4 wle watchdog load enable . this ?g must be set by software prior to loading t3 (watchdog timer). it is cleared when t3 is loaded. 3 gf1 general purpose ?g bits . 2 gf0 1pd power-down mode select . setting this bit activates power-down mode. it can only be set if the watchdog timer enable bit ?de?is set to logic 0. 0 idl idle mode select . setting this bit activates the idle mode.
2000 jul 26 24 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12 can, controller area network controller area network is the definition of a high performance communication protocol for serial data communication. the can controller circuitry is designed to provide a full implementation of the can-protocol according to the can specification version 2.0 b. microcontroller including this on-chip can controller are used to build powerful local networks, both for general industrial and automotive environments. the result is a strongly reduced wiring harness and enhanced diagnostic and supervisory capabilities. the P8XC591 includes the same functions known from the sja1000 stand-alone can controller from philips semiconductors with the following improvements: ? enhanced receive interrupt ? enhanced acceptance filter 8 filter for standard frame formats 4 filter for extended formats ?hange on the fly?feature. 12.1 features of the pelican controller 12.1.1 g eneral can features ? can 2.0b protocol compatibility ? multi-master architecture ? bus access priority determined by the message identifier (11 bit or 29 bit) ? non destructive bit-wise arbitration ? guaranteed latency time for high priority messages ? programmable transfer rate (up to 1mbit/s) ? multicast and broadcast message facility ? data length from 0 up to 8 bytes ? powerful error handling capability ? non-return-to-zero (nrz) coding/decoding with bit-stuffing ? suitable for use in a wide range of networks including sae? network classes a, b, c. 12.1.2 p8 x c591 p eli can features ( additional to can 2.0b) ? supports 11-bit identifier as well as 29-bit identifier ? bit rates up to 1 mbit/s ? error counters with read / write access ? programmable error warning limit ? error code capture with detailed bit position ? arbitration lost interrupt with detailed bit position ? single shot transmission (no re-transmission) ? listen only mode (no acknowledge, no active error flags) ? hot plugging support (software driven bit rate detection) ? extended receive buffer (fifo, 64 byte) ? receive buffer level sensitive receive interrupt ? high priority acceptance filters for receive interrupt ? acceptance filters with ?hange on the fly?feature ? reception of ?wn messages (self reception request) ? programmable can output driver configuration.
2000 jul 26 25 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.2 pelican structure a 80c51 cpu interface connects the pelican to the internal bus of the P8XC591 microcontroller. via five special function registers canadr, candat, canmod, cansta and cancon the cpu has access to the pelican. the sfr will described later on. fig.10 block diagram of the pelican. handbook, full pagewidth mhi010 pelican core block message buffer error management logic transmit buffer control address/data receive fifo acceptance filter bit timing logic transmit management logic interface management logic tx rx bit stream processor txdc rxdc
2000 jul 26 26 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.2.1 i nterface m anagement l ogic (iml) the interface management logic interprets commands from the cpu, controls addressing of the can registers and provides interrupts and status information to the cpu. additionally it drives the universal interface of the pelican. 12.2.2 t ransmit b uffer (txb) the transmit buffer is an interface between the cpu and the bit stream processor (bsp) and is able to store a complete can message which should be transmitted over the can network. the buffer is 13 bytes long, written by the cpu and read out by the bsp or the cpu itself. 12.2.3 r eceive b uffer (rxb, rxfifo) the receive buffer is an interface between the acceptance filter and the cpu and stores the received and accepted messages from the can bus line. the receive buffer (rxb) represents a cpu-accessible 13-byte-window of the receive fifo (rxfifo), which has a total length of 64 bytes. with the help of this fifo the cpu is able to process one message while other messages are being received. 12.2.4 a cceptance f ilter (acf) the acceptance filter compares the received identifier with the acceptance filter table contents and decides whether this message should be accepted or not. in case of a positive acceptance test, the complete message is stored in the rxfifo. the acf contains 4 independent acceptance filter banks supporting extended and standard can frames with ?hange on the fly?feature. 12.2.5 b it s tream p rocessor (bsp) the bit stream processor is a sequencer, controlling the data stream between the transmit buffer, rxfifo and the can-bus. it also performs the error detection, arbitration, stuffing and error handling on the can bus. 12.2.6 e rror m anagement l ogic (eml) the eml is responsible for the error confinement of the transfer-layer modules. it gets error announcements from the bsp and then informs the bsp and iml about error statistics. 12.2.7 b it t iming l ogic (btl) the bit timing logic monitors the serial can bus line and handles the bus line-related bit timing. it synchronizes to the bit stream on the can bus on a ?ecessive?to ?ominant?bus line transition at the beginning of a message (hard synchronization) and resynchronizes on further transitions during the reception of a message (soft synchronization). the btl also provides programmable time segments to compensate for the propagation delay times and phase shifts (e.g., due to oscillator drifts) and to define the sampling time and the number of samples to be taken within a bit time. 12.2.8 t ransmit m anagement l ogic (tml) the transmit management logic provides the driver signals for the push-pull can tx transistor stage. depending on the programmable output driver configuration the external transistors are switched on or off. additionally a short circuit protection and the asynchronous float on hardware reset is performed here.
2000 jul 26 27 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.3 communication between pelican controller and cpu a 80c51 cpu interface connects the pelican to the internal bus of an 80c51 microcontroller. special function registers, allows a smart and fast access to the pelican registers and ram area. because of the big address range to be supported, an indirect pointer based addressing is included allowing a fast register access with address autoincrement mode. this reduces the needed number of special function registers to an amount of 5. ? five special function registers (sfrs) ? register address generation in auto-increment mode ? access to the complete address range of the pelican fig.11 cpu to can interfacing. handbook, full pagewidth mhi020 data 80c51 core write read sfrs pelican address candat canadr interface can controller cansta cancon canmod 12.3.1 s pecial f unction r egisters via the five special function registers canadr, candat, canmod, cansta and cancon the cpu has access to the pelican block. note that cancon and cansta have different registers mapped depending on the direction of the access. the pelican registers may be accessed in two different ways. the most important registers, which should support software polling or are controlling major can functions are accessible directly as separate sfrs. other parts of the pelican block are accessible using an indirect pointer mechanism. in order to achieve a high data throughput even if the indirect access is used, an address auto-increment feature is included here.
2000 jul 26 28 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 10 can special function registers sfr access pelican reg. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr addr canadr read/ write - cana7 cana6 cana5 cana4 cana3 cana2 cana1 cana0 c1 candat read/ write - cand7 cand6 cand5 cand4 cand3 cand2 cand1 cand0 c2 canmod read/ write mode tm ripm rpm sm ? stm lom rm c4 cansta read status bs es ts rs tcs tbs dos rbs c0 write interrupt enable beie alie epie wuie doie eie tie rie cancon read interrupt bei ali epi wui doi ei ti ri c3 write command - - - srr cdo rrb at tr 12.3.2 canadr this read/write register defines the address of one of the pelican internal registers to be accessed via candat. it could be interpreted as a pointer to the pelican. the read and write access to the pelican block register is performed using the candat register. with the implemented auto address increment mode a fast stack-like reading and writing of can controller internal registers is provided. if the currently defined address within canadr is above or equal to 32 decimal, the content of canadr is incremented automatically after any read or write access to candat. for instance, loading a message into the transmit buffer can be done by writing the first transmit buffer address (112 decimal) into canadr and then moving byte by byte of the message to candat. incrementing canadr beyond ffh resets canadr to 00h. in case canadr is below 32 decimal, there is no automatic address incrementation performed. canadr keeps its value even if candat is accessed for reading or writing. this is to allow polling of registers in the lower address space of the pelican controller. 12.3.3 candat r egister candat is implemented as a read/write register. the special function register candat appears as a port to the can controller? internal register (memory location) being selected by canadr. reading or writing candat is effectively an access to that pelican internal register, which is selected by canadr. candat is implemented as a read/write register. note that any access to this register automatically increments canadr if the current address within canadr is above or equal to 32 decimal. 12.3.4 canmod with a read or write access to canmod the mode register of the pelican is accessed directly. the mode register is located at address 00h within the pelican block. 12.3.5 cansta the cansta sfr provides a direct access to the status register of the pelican as well as to the interrupt enable register, depending on the direction of the access. reading cansta is an access to the status register of the pelican (address 2). when writing to cansta the interrupt enable register is accessed (address 4). 12.3.6 cancon the cancon sfr provides a direct access to the interrupt register of the pelican as well as to the command register, depending on the direction of the access. when reading cancon the interrupt register of the pelican is accessed (address 3), while writing to cancon means an access to the command register (address 1).
2000 jul 26 29 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.4 register and message buffer description 12.4.1 a ddress l ayout the pelican internal registers appear to the host cpu as on-chip memory mapped peripheral registers. because the pelican can operate in different modes (operating / reset, see also mode register), one have to distinguish between different internal address definitions. starting from can address 128 the complete internal fifo ram is mapped to the cpu interface. table 11 address allocation can addr. operating mode reset mode read write read write 0 mode mode mode mode 1 (00) command (00) command 2 status - status - 3 interrupt - interrupt - 4 interrupt enable interrupt enable interrupt enable interrupt enable 5 rx interrupt level rx interrupt level rx interrupt level rx interrupt level 6 bus timing 0 - bus timing 0 bus timing 0 7 bus timing 1 - bus timing 1 bus timing 1 8 see note 2 --- 9 rx message counter - rx message counter - 10 rx buffer start address - rx buffer start address - 11 arbitration lost capture - arbitration lost capture - 12 error code capture - error code capture - 13 error warning limit error warning limit error warning limit error warning limit 14 rx error counter - rx error counter rx error counter 15 tx error counter - tx error counter tx error counter 16 to 28 reserved (00) - reserved (00) - 29 acf mode - acf mode acf mode 30 acf enable acf enable acf enable acf enable 31 acf priority acf priority acf priority acf priority 32 b a n k 1 acceptance code 0 acceptance code 0 acceptance code 0 acceptance code 0 33 acceptance code 1 acceptance code 1 acceptance code 1 acceptance code 1 34 acceptance code 2 acceptance code 2 acceptance code 2 acceptance code 2 35 acceptance code 3 acceptance code 3 acceptance code 3 acceptance code 3 36 acceptance mask 0 acceptance mask 0 acceptance mask 0 acceptance mask 0 37 acceptance mask 1 acceptance mask 1 acceptance mask 1 acceptance mask 1 38 acceptance mask 2 acceptance mask 2 acceptance mask 2 acceptance mask 2 39 acceptance mask 3 acceptance mask 3 acceptance mask 3 acceptance mask 3 40 b a n k 2 acceptance code 0 acceptance code 0 acceptance code 0 acceptance code 0 41 acceptance code 1 acceptance code 1 acceptance code 1 acceptance code 1 42 acceptance code 2 acceptance code 2 acceptance code 2 acceptance code 2 43 acceptance code 3 acceptance code 3 acceptance code 3 acceptance code 3 44 acceptance mask 0 acceptance mask 0 acceptance mask 0 acceptance mask 0 45 acceptance mask 1 acceptance mask 1 acceptance mask 1 acceptance mask 1 46 acceptance mask 2 acceptance mask 2 acceptance mask 2 acceptance mask 2 47 acceptance mask 3 acceptance mask 3 acceptance mask 3 acceptance mask 3
2000 jul 26 30 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 48 b a n k 3 acceptance code 0 acceptance code 0 acceptance code 0 acceptance code 0 49 acceptance code 1 acceptance code 1 acceptance code 1 acceptance code 1 50 acceptance code 2 acceptance code 2 acceptance code 2 acceptance code 2 51 acceptance code 3 acceptance code 3 acceptance code 3 acceptance code 3 52 acceptance mask 0 acceptance mask 0 acceptance mask 0 acceptance mask 0 53 acceptance mask 1 acceptance mask 1 acceptance mask 1 acceptance mask 1 54 acceptance mask 2 acceptance mask 2 acceptance mask 2 acceptance mask 2 55 acceptance mask 3 acceptance mask 3 acceptance mask 3 acceptance mask 3 56 b a n k 4 acceptance code 0 acceptance code 0 acceptance code 0 acceptance code 0 57 acceptance code 1 acceptance code 1 acceptance code 1 acceptance code 1 58 acceptance code 2 acceptance code 2 acceptance code 2 acceptance code 2 59 acceptance code 3 acceptance code 3 acceptance code 3 acceptance code 3 60 acceptance mask 0 acceptance mask 0 acceptance mask 0 acceptance mask 0 61 acceptance mask 1 acceptance mask 1 acceptance mask 1 acceptance mask 1 62 acceptance mask 2 acceptance mask 2 acceptance mask 2 acceptance mask 2 63 acceptance mask 3 acceptance mask 3 acceptance mask 3 acceptance mask 3 64 to 95 reserved (00) - reserved (00) - (sff) (eff) (sff) (eff) (sff) (eff) 96 rx frame info rx frame info - rx frame info rx frame info rx frame info rx frame info 97 rx identi?r 1 rx identi?r 1 - rx identi?r 1 rx identi?r 1 rx identi?r 1 rx identi?r 1 98 rx identi?r 2 rx identi?r 2 - rx identi?r 2 rx identi?r 2 rx identi?r 2 rx identi?r 2 99 rx data 1 rx identi?r 3 - rx data 1 rx identi?r 3 rx data 1 rx identi?r 3 100 rx data 2 rx identi?r 4 - rx data 2 rx identi?r 4 rx data 2 rx identi?r 4 101 rx data 3 rx data 1 - rx data 3 rx data 1 rx data 3 rx data 1 102 rx data 4 rx data 2 - rx data 4 rx data 2 rx data 4 rx data 2 103 rx data 5 rx data 3 - rx data 5 rx data 3 rx data 5 rx data 3 104 rx data 6 rx data 4 - rx data 6 rx data 4 rx data 6 rx data 4 105 rx data 7 rx data 5 - rx data 7 rx data 5 rx data 7 rx data 5 106 rx data 8 rx data 6 - rx data 8 rx data 6 rx data 8 rx data 6 107 (fifo ram) (1) rx data 7 - (fifo ram) (1) rx data 7 (fifo ram) (1) rx data 7 108 (fifo ram) (1) rx data 8 - (fifo ram) (1) rx data 8 (fifo ram) (1) rx data 8 109 to 111 reserved (00) - reserved (00) - (sff) (eff) (sff) (eff) (sff) (eff) 112 tx frame info tx frame info tx frame info tx frame info tx frame info tx frame info tx frame info tx frame info 113 tx identi?r 1 tx identi?r 1 tx identi?r 1 tx identi?r 1 tx identi?r 1 tx identi?r 1 tx identi?r 1 tx identi?r 1 114 tx identi?r 2 tx identi?r 2 tx identi?r 2 tx identi?r 2 tx identi?r 2 tx identi?r 2 tx identi?r 2 tx identi?r 2 can addr. operating mode reset mode read write read write
2000 jul 26 31 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 notes 1. these address locations reflect the fifo ram space behind the current message. the contents are randomly after power-up and contain the beginning of the next message that is received after the current one. if no further message is received, parts of old messages may occur here. 2. register at address 8 performs no system function; reserved for future use. 115 tx data 1 tx identi?r 3 tx data 1 tx identi?r 3 tx data 1 tx identi?r 3 tx data 1 tx identi?r 3 116 tx data 2 tx identi?r 4 tx data 2 tx identi?r 4 tx data 2 tx identi?r 4 tx data 2 tx identi?r 4 117 tx data 3 tx data 1 tx data 3 tx data 1 tx data 3 tx data 1 tx data 3 tx data 1 118 tx data 4 tx data 2 tx data 4 tx data 2 tx data 4 tx data 2 tx data 4 tx data 2 119 tx data 5 tx data 3 tx data 5 tx data 3 tx data 5 tx data 3 tx data 5 tx data 3 120 tx data 6 tx data 4 tx data 6 tx data 4 tx data 6 tx data 4 tx data 6 tx data 4 121 tx data 7 tx data 5 tx data 7 tx data 5 tx data 7 tx data 5 tx data 7 tx data 5 122 tx data 8 tx data 6 tx data 8 tx data 6 tx data 8 tx data 6 tx data 8 tx data 6 123 (txb memory) tx data 7 (txb memory) tx data 7 (txb memory) tx data 7 (txb memory) tx data 7 124 (txb memory) tx data 8 (txb memory) tx data 8 (txb memory) tx data 8 (txb memory) tx data 8 125 to 127 general purpose ram general purpose ram general purpose ram general purpose ram 128 ... 191 internal ram address 0 (fifo) internal ram address 63 (fifo) - - - internal ram address 0 (fifo) internal ram address 63 (fifo) internal ram address 0 (fifo) internal ram address 63 (fifo) can addr. operating mode reset mode read write read write
2000 jul 26 32 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5 can registers 12.5.1 r eset v alues detection of a set reset mode bit results in aborting the current transmission / reception of a message and entering the reset mode. on the ??to-??transition of the reset mode bit, the can controller returns to the mode defined within the mode register. table 12 reset mode con?uration ??means that the values of these registers or bits are not in?enced. addr. register bit symbol name reset by hardware setting mod.0 by software or due to bus-off 0 mode mod.7 mod.6 mod.5 mod.4 mod.3 mod.2 mod.1 mod.0 tm - rpm sm - stm lom rm test mode - receive polarity mode sleep mode - self test mode listen only mode reset mode 0 (disabled) x (reserved) 0 (active low) 0 (wake-up) 0 (reserved) 0 (normal) 0 (normal) 1 (present) 0 (disabled) x (reserved) 0 (active high) 0 (wake-up) 0 (reserved) x no change x no change 1 (present) 1 command cmr.7-5 cmr.4 cmr.3 cmr.2 cmr.1 cmr.0 - srr cdo rrb at tr - self reception request clear data overrun release receive buffer abort transmission transmission request 0 (reserved) 0 (absent) 0 (no action) 0 (no action) 0 (absent) 0 (absent) 0 (reserved) 0 (absent) 0 (no action) 0 (no action) 0 (absent) 0 (absent) 2 status sr.7 sr.6 sr.5 sr.4 sr.3 sr.2 sr.1 sr.0 bs es ts rs tcs tbs dos rbs bus status error status transmit status receive status transmission complete status transmit buffer status data overrun status receive buffer status 0 (bus-on) 0 (ok) 1 (wait idle) 1 (wait idle) 1 (complete) 1 (released) 0 (absent) 0 (empty) 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) x no change (1) 0 (reset) 0 (reset) 3 interrupt ir.7 ir.6 ir.5 ir.4 ir.3 ir.2 ir.1 ir.0 bei ali epi wui doi ei ti ri bus error interrupt arbitration lost interrupt error passive interrupt wake-up interrupt data overrun interrupt error warning interrupt transmit interrupt receive interrupt 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) x no change (1) 0 (reset) 0 (reset) 0 (reset) 0 (reset) x no change 0 (reset) 0 (reset) 4 interrupt enable ier.7 ier.6 ier.5 ier.4 ier.3 ier.2 ier.1 ier.0 beie alie epie wuie doie eie tie rie bus error interrupt enable arbitr. lost interrupt enable error passive interrupt wake-up interrupt enable data overrun interrupt enable error warning interrupt enable transmit interrupt enable receive interrupt enable x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change 5 rx interrupt level - ril rx interrupt level 00000000b x no change 6 bus timing 0 btr0.7 btr0.6 btr0.5 btr0.4 btr0.3 btr0.2 btr0.1 btr0.0 sjw.1 sjw.0 brp.5 brp.4 brp.3 brp.2 brp.1 brp.0 synchronization jump width 1 synchronization jump width 0 baud rate prescaler 5 baud rate prescaler 4 baud rate prescaler 3 baud rate prescaler 2 baud rate prescaler 1 baud rate prescaler 0 x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change 7 bus timing 1 btr1.7 btr1.6 btr1.5 btr1.4 btr1.3 btr1.2 btr1.1 btr1.0 sam tseg2.2 tseg2.1 tseg2.0 tseg1.3 tseg1.2 tseg1.1 tseg1.0 sampling time segment 2.2 time segment 2.1 time segment 2.0 time segment 1.3 time segment 1.2 time segment 1.1 time segment 1.0 x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change
2000 jul 26 33 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 notes 1. on bus-off the error warning interrupt is set, if enabled. 2. if the reset mode was entered due to a bus-off condition, the receive error counter is cleared and the transmit error counter is initialized to 127 to count-down the can-defined bus-off recovery time consisting of 128 occurrences of 11 consecutive recessive bits. 3. internal read/write pointers of the rxfifo are reset to their initial values. a subsequent read access to the rxb would show undefined data values (parts of old messages). if a message is transmitted, this message is written in parallel to the receive buffer. a receive interrupt is generated only, if this transmission was forced by the self reception request. so, even if the receive buffer is empty, the last transmitted message may be read from the receive buffer until it is overridden by the next received or transmitted message. upon a hardware reset, the rxfifo pointers are reset to the physical ram address ?? setting mod.0 by software or due to the bus-off event will reset the rxfifo pointers to the currently valid fifo start address (rbsa register) which is different from the ram address ? after the first release receive buffer command. 9 rx message counter ? rmc rx message counter 0 0 10 rx buffer start address ? rbsa rx buffer start address 00000000 b x no change 11 arbitr. lost capture ? alc arbitration lost capture 0 x no change 12 error code capture ? ecc error code capture 0 x no change 13 error warning limit ? ewlr error warning limit register 96d x no change 14 rx error counter ? rxerr receive error counter 0 (reset) x no change (2) 15 tx error counter ? txerr transmit error counter 0 (reset) x no change (2) 29 acf mode acfmod.7 acfmod.6 acfmod.5 acfmod.4 acfmod.3 acfmod.2 acfmod.1 acfmod.0 mformatb4 amodeb4 mformatb3 amodeb3 mformatb2 amodeb2 mformatb1 amodeb1 message format bank4 accept. filt. mode bank message format bank3 accept. filt. mode bank3 message format bank2 accept. filt. mode bank2 message format bank1 accept. filt. mode bank1 0 (sff) 0 (dual) 0 (sff) 0 (dual) 0 (sff) 0 (dual) 0 (sff) 0 (dual) x no change x no change x no change x no change x no change x no change x no change x no change 30 acf enable acfen.7 acfen.6 acfen.5 acfen.4 acfen.3 acfen.2 acfen.1 acfen.0 b4f2en b4f1en b3f2en b3f1en b2f2en b2f1en b1f2en b1f1en bank 4 filter 2 enable bank 4 filter 1 enable bank 3 filter 2 enable bank 3 filter 1 enable bank 2 filter 2 enable bank 2 filter 1 enable bank 1 filter 2 enable bank 1 filter 1 enable x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change 31 acf priority acfprio.7 acfprio.6 acfprio.5 acfprio.4 acfprio.3 acfprio.2 acfprio.1 acfprio.0 b4f2prio b4f1prio b3f2prio b3f1prio b2f2prio b2f1prio b1f2prio b1f1prio bank 4 filter 2 priority bank 4 filter 1 priority bank 3 filter 2 priority bank 3 filter 1 priority bank 2 filter 2 priority bank 2 filter 1 priority bank 1 filter 2 priority bank 1 filter 1 priority x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change x no change 32 to 35 bank 1 acr 0 to 3 ? acr0 to acr3 acceptance code register x no change x no change 36 to 39 amr 0 to 3 ? amr0 to amr3 acceptance mask register x no change x no change 40 to 43 bank 2 acr 0 to 3 ? acr0 to acr3 acceptance code register x no change x no change 44 to 47 amr 0 to 3 ? amr0 to amr3 acceptance mask register x no change x no change 48 to 51 bank 3 acr 0 to 3 ? acr0 to acr3 acceptance code register x no change x no change 52 to 55 amr 0 to 3 ? amr0 to amr3 acceptance mask register x no change x no change 56 to 59 bank 4 acr 0 to 3 ? acr0 to acr3 acceptance code register x no change x no change 60 to 63 amr 0 to 3 ? amr0 to amr3 acceptance mask register x no change x no change 96 to 108 rx buffer ? rxb receive buffer x empty (3) x empty (3) 112 to 124 tx buffer ? txb transmit buffer x no change x no change 125 to 127 general purpose ram ?? general purpose ram x no change x no change addr. register bit symbol name reset by hardware setting mod.0 by software or due to bus-off
2000 jul 26 34 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.2 m ode r egister (mod) the contents of the mode register are used to change the behaviour of the can controller. bits may be set or reset by the cpu that uses the mode register as a read / write memory. reserved bits are read as ?? table 13 mode register (mod) can addr. 0 bit interpretation notes 1. a write access to the bits mod.1, mod.2, mod.5, mod.6 and mod.7 is possible only, if the reset mode is entered previously. 2. the pelican block will enter sleep mode, if the sleep mode bit is set ??(sleep), there is no bus activity and no interrupt is pending. setting of sm with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. the can controller will wake up if sm is set low (wake-up) or there is bus activity. on wake-up, a wake-up interrupt is generated. a sleeping can controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits (bus-free sequence). note that setting of sm is not possible in reset mode. after clearing of reset mode, setting of sm is possible first, when bus-free is detected again. 3. this mode of operation forces the can controller to be error passive. message transmission is not possible. the listen only mode can be used e.g. for software driven bit rate detection and ?ot plugging? bit symbol name value function mod.7 tm test mode; note 1 1 (activated) the txdc pin will re?ct the bit, detected on rxdc pin, with the next positive edge of the system clock. the rpm bit has no in?ence within this mode. 0 (disabled) mod.6 ripm reserved. ?? mod.5 rpm receive polarity mode 1 (high active) 0 (low active) rxd inputs are active high (dominant = 1). rxd inputs are active low (dominant = 0). mod.4 sm sleep mode; note 2 1 (high active)) the can controller enters sleep mode if no can interrupt is pending and there is no bus activity. 0 (low active) mod.3 ? reserved ?? mod.2 stm self test mode; note 1 1 (self test) in this mode a full node test is possible without any other active node on the bus using the self reception request command. the can controller will perform a successful transmission, even if there is no acknowledge received. 0 (normal) an acknowledge is required for successful transmission. mod.1 lom listen only mode; notes 1 and 3 1 (reset) in this mode the can would give no acknowledge to the can bus, even if a message is received successfully. no active error ?gs are driven to the bus. the error counters are stopped at the current value. 0 (normal) normal communication. mod.0 rm reset mode; note 4 1 (reset) setting the reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0 (normal) on the??to-??transition of the reset mode bit, the can controller returns to the operating mode.
2000 jul 26 35 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 4. during a hardware reset or when the bus status bit is set ? (bus-off), the reset mode bit is set ? (present). after the reset mode bit is set ??the can controller will wait for: a) one occurrence of bus-free signal (11 recessive bits), if the preceding reset has been caused by hardware reset or a cpu-initiated reset. b) 128 occurrences of bus-free, if the preceding reset has been caused by a can controller initiated bus-off, before re-entering the bus-on mode 12.5.3 c ommand r egister (cmr) the contents of the command register are used to change the behaviour of the can controller. control bits may be set or reset by the cpu which uses the command register as a write only memory. table 14 command register (cmr) can addr. 1, bit interpretation notes 1. upon self reception request a message is transmitted and simultaneously received if the acceptance filter is set to the corresponding identifier. a receive and a transmit interrupt will indicate correct self reception. (see also self test mode in mode register). 2. this command bit is used to clear the data overrun condition signalled by the data overrun status bit. as long as the data overrun status bit is set no further data overrun interrupt is generated. 3. after reading the contents of the receive buffer, the cpu can release this memory space of the rxfifo by setting the release receive buffer bit ?? this may result in another message becoming immediately available within the receive buffer. if there is no other message available, the receive interrupt bit is reset. the receive interrupt is also reset in case there is no ?igh priority message available within the fifo (see acceptance filter description) and the available message bytes are equal to or less to the specified value within the receive interrupt level register. if the rrb command is given, it will take at least 2 internal clock cycles before a new receive interrupt is generated and rx buffer start address is updated. 4. the abort transmission bit is used when the cpu requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. a transmission already in progress is not stopped. in order to see if the original message had been either transmitted successfully or aborted, the transmission complete status bit should be checked. this should be done after the transmit buffer status bit has been set ? or a transmit interrupt has been generated. bit symbol name value function cmr.7 to cmr.5 - reserved - cmr.4 srr self reception request; notes 1 and 6 1 (present) a message shall be transmitted and received simultaneously. 0 (absent) cmr.3 cdo clear data overrun; note 2 1 (clear) the data overrun status bit is cleared. 0 (no action) cmr.2 rrb release receive buffer; note 3 1 (released) the receive buffer, representing the message memory space in the rxfifo is released. 0 (no action) cmr.1 at abort transmission; notes 4 and 6 1 (present) if not already in progress, a pending transmission request is cancelled. 0 (absent) cmr.0 tr transmission request; notes 5 and 6 1 (present) a message shall be transmitted. 0 (absent)
2000 jul 26 36 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 5. if the transmission request or the self reception request bit was set ??in a previous command, it cannot be cancelled by resetting the bits. the requested transmission may only be cancelled by setting the abort transmission bits. 6. setting the command bits cmr.0 and cmr.1 simultaneously results in transmitting a message once. no re-transmission will be performed in case of an error or arbitration lost (single shot transmission). setting the command bits cmr.4 and cmr.1 simultaneously results in sending the transmit message once using the self reception feature. no re-transmission will be performed in case of an error or arbitration lost. setting the command bits cmr.0, cmr.1 and cmr.4 simultaneously results in transmitting a message once as described for cmr.0 and cmr.1. the moment the transmit status bit is set within the status register, the internal transmission request bit is cleared automatically. setting cmr.0 and cmr.4 simultaneously will ignore the set cmr.4 bit. 12.5.4 s tatus r egister (sr) the content of the status register reflects the status of the can controller. the status register appears to the cpu as a read only memory. table 15 status register (sr) can addr. 2, bit interpretation bit symbol name value function sr.7 bs bus status; note 1 1 (bus-off) the can controller is not involved in bus activities. 0 (bus-on) the can controller is involved in bus activities sr.6 es error status; note 2 1 (error) at least one of the error counters has reached or exceeded the cpu warning limit. 0 (ok) both error counters are below the warning limit. sr.5 ts transmit status; note 3 1 (transmit) the can controller is transmitting a message. 0 (idle) sr.4 rs receive status; note 3 1 (receive) the can controller is receiving a message. 0 (idle) sr.3 tcs transmission complete status; note 4 1 (complete) last requested transmission has been successfully completed. 0 (incomplete) previously requested transmission is not yet completed. sr.2 tbs transmit buffer status; note 5 1 (released) the cpu may write a message into the transmit buffer. 0 (locked) the cpu cannot access the transmit buffer. a message is either waiting for transmission or is in transmitting process. sr.1 dos data overrun status; note 6 1 (overrun) a message was lost because there was not enough space for that message in the rxfifo. 0 (absent) no data overrun has occurred since the last clear data overrun command was given sr.0 rbs receive buffer status; note 7 1 (full) one or more complete messages are available in the rxfifo. 0 (empty) no message is available.
2000 jul 26 37 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 notes to table 15 : 1. when the transmit error counter exceeds the limit of 255, the bus status bit is set ? (bus-off), the can controller will set the reset mode bit ??(present), an error warning and a bus error interrupt is generated, if enabled. the transmit error counter is set to ?27? it will stay in this mode until the cpu clears the reset request bit. once this is completed the can controller will wait the minimum protocol-defined time (128 occurrences of the bus-free signal) counting down the transmit error counter. after that the bus status bit is cleared (bus-on), the error status bit is set ? (ok), the error counters are reset and an error interrupt is generated, if enabled. reading the tx error counter during this time gives information about the status of the bus-off recovery. 2. errors detected during reception or transmission will effect the error counters according to the can specification. the error status bit is set when at least one of the error counters has reached or exceeded the cpu warning limit of 96. an error interrupt is generated, if enabled. 3. if both the receive status and the transmit status bits are ??(idle) the can-bus is idle. 4. the transmission complete status bit is set ??(incomplete) whenever the transmission request bit or the self reception request bit is set ?? the transmission complete status bit will remain ? until a message is transmitted successfully. 5. if the cpu tries to write to the transmit buffer when the transmit buffer status bit is ? (locked), the written byte will not be accepted and will be lost without this being signalled. 6. when a message that is to be received has passed the acceptance filter successfully, the can controller needs space in the rxfifo to store the message descriptor and for each data byte which has been received. if there is not enough space to store the massage, that message is dropped and the data overrun condition is indicated to the cpu at the moment this message becomes valid. if this message is not completed (e.g. because of an error), no overrun condition is indicated. 7. after reading all messages within the rxfifo and releasing their memory space with the command release receive buffer this bit is cleared.
2000 jul 26 38 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.5 i nterrupt r egister (ir) the interrupt register allows the identification of an interrupt source. when one or more bits of this register are set, a can interrupt will be indicated to the cpu. after this register is read by the cpu all bits are reset except of the receive interrupt bit. the interrupt register appears to the cpu as a read only memory. table 16 interrupt register (ir) can addr. 3, bit interpretation bit symbol name value function ir.7 bei bus error interrupt 1 (set) this bit is set when the can controller detects an error on the can bus and the beie bit is set within the interrupt enable register. after a bus error interrupt event this interrupt is locked until the error code capture register is read out once. 0 (reset) ir.6 ali arbitration lost interrupt 1 (set) this bit is set when the can controller has lost arbitration and becomes a receiver and the alie bit is set within the interrupt enable register. after an arbitration lost interrupt event this interrupt is locked until the arbitration lost capture register is read out once. 0 (reset) ir.5 epi error passive interrupt 1 (set) this bit is set whenever the can controller has reached the error passive status (at least one error counter exceeds the can protocol de?ed level of 127) or if the can controller is in error passive status and enters the error active status again and the epie bit is set within the interrupt enable register. 0 (reset) ir.4 wui wake-up interrupt; note 1 1 (set) this bit is set when the can controller is sleeping and bus activity is detected and the wuie bit is set within the interrupt enable register. 0 (reset) ir.3 doi data overrun interrupt 1 (set) this bit is set on a 0-to-1 change of the data overrun status bit, when the data overrun interrupt enable is set to ? (enabled). 0 (reset) ir.2 ei error interrupt 1 (set) this bit is set on every change (set and clear) of either the error status or bus status bits if the error interrupt enable is set to ??(enabled). 0 (reset) ir.1 ti transmit interrupt; note 2 1 (set) this bit is set whenever the transmit buffer status changes from ??to ??(released) and transmit interrupt enable is set to ??(enabled). 0 (reset) ir.0 ri receive interrupt; note 2 1 (set) this bit is set whenever the rxfifo is ?led with more bytes than speci?d in the rx interrupt level register or a message has passed an acceptance ?ter which is set to ?igh priority and the rie bit is set within the interrupt enable register. 0 (reset)
2000 jul 26 39 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 notes to table 16 : 1. a wake-up interrupt is also generated, if the cpu tries to set the sleep bit while the can controller is involved in bus activities or a can interrupt is pending. 2. in order to support high priority messages, the receive interrupt is forced immediately upon a received message, which has passed successfully an acceptance filter with high priority (see acceptance filter section). as long as only messages are received via low priority acceptance filters, the receive interrupt is not forced until the fifo is filled with more bytes than programmed in the rx interrupt level register. the receive interrupt bit is not cleared upon a read access to the interrupt register. giving the command ?elease receive buffer?will clear ri temporarily. if there is another message available within the fifo after the release command, ri is set again. otherwise ri keeps cleared. 12.5.6 i nterrupt e nable r egister (ier) the register allows to enable different types of interrupt sources which are signalled to the cpu. the interrupt enable register appears to the cpu as a read / write memory. table 17 interrupt enable register (ier) can addr. 4, bit interpretation bit symbol name value function ier.7 beie bus error interrupt enable 1 (enabled) if a bus error has been detected, the can controller requests the respective interrupt. 0 (disabled) ier.6 alie arbitration lost interrupt enable 1 (enabled) if the can controller has lost arbitration, the respective interrupt is requested. 0 (disabled) ier.5 epie error passive interrupt enable 1 (enabled) if the error status of the can controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0 (disabled) ier.4 wuie wake-up interrupt enable 1 (enabled) if the sleeping can controller wakes up, the respective interrupt is requested. 0 (disabled) ier.3 doie data overrun interrupt enable 1 (enabled) if the data overrun status bit is set (see status register), the can controller requests the respective interrupt. 0 (disabled) ier.2 eie error interrupt enable 1 (enabled) if the error or bus status change (see status register), the can controller requests the respective interrupt. 0 (disabled) ier.1 tie transmit interrupt enable 1 (enabled) when a message has been successfully transmitted or the transmit buffer is accessible again, (e.g. after an abort transmission command) the can controller requests the respective interrupt. 0 (disabled) ier.0 rie receive interrupt enable 1 (enabled) when the receive buffer status is ?ull?the can controller requests the respective interrupt. 0 (disabled)
2000 jul 26 40 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.7 rx i nterrupt l evel (ril) the ril register is used to define the receive interrupt level for the rxfifo. a receive interrupt is generated if the number of valid can message bytes in the rxfifo exceeds the level specified in this register. note that receive interrupts are only generated if complete messages have been received. if ril is set to 00 the pelican functions like the receive interrupt behaviour of the sja1000. table 18 bit interpretation of the rx interrupt level (ril) 12.5.8 b us t iming r egister 0 (btr0) the contents of the bus timing register 0 defines the values of the baud rate prescaler (brp) and the synchronization jump width (sjw). this register can be accessed (read/write) if the reset mode is active. in operating mode, this register is read only. table 19 bus timing register 0 (btr0) (can address 6) 12.5.8.1 baud rate prescaler (brp) the period of the can system clock t scl is programmable and determines the individual bit timing. the can system clock is calculated using the following equation: 12.5.8.2 synchronization jump width (sjw) to compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must resynchronize on any relevant signal edge of the current transmission. the synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened by one resynchronization: can addr. 5 rx interrupt level (ril) 76543 2 1 0 ril.7 ril.6 ril.5 ril.4 ril.3 ril.2 ril.1 ril.0 7 6 5 4 3 2 1 0 sjw.1 sjw.0 brp.5 brp.4 brp.3 brp.2 brp.1 brp.0 t scl t clk 32 brp.5 16 brp.4 8 brp.3 4 brp.2 2 brp.1 brp.0 1 ++ + + + + ( ) = t clk time period of the cs system clock 1 f clk --------------- == t sjw t scl 2 sjw.1 sjw.0 1 ++ () =
2000 jul 26 41 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.9 b us t iming r egister 1 (btr1) the contents of bus timing register 1 defines the length of the bit period, the location of the sample point and the number of samples to be taken at each bit time. this register can be accessed (read/write) if the reset mode is active. in operating mode, this register is read only. table 20 bus timing register 1 (btr1) (can address 7) 12.5.9.1 sampling (sam) table 21 sampling (sam) 12.5.9.2 time segment 1 (tseg1) and time segment 2 (tseg2) tseg1 and tseg2 determine the number of clock cycles per bit period and the location of the sample point: 7 6 5 4 3 2 1 0 sam tseg2.2 tseg2.1 tseg2.0 tseg1.3 tseg1.2 tseg1.1 tseg1.0. bit value function sam 1 (triple) the bus is sampled three times -> recommended for low/medium speed buses (class a and b) where ?tering spikes on the bus-line is bene?ial 0 (once) the bus is sampled once -> recommended for high speed buses (sae class c) t syncseg 1t scl = t tseg1 t scl 8 tseg1.3 4 tseg1.2 2 tseg1.1 tseg1.0 1 ++ + + () = t tseg2 t scl 4 tseg2.2 2 tseg2.1 tseg2.0 1 ++ + () = handbook, full pagewidth mhi011 t scl t syncseg sync. seg. can: c: sync. seg. t tseg1 t tseg2 tseg1 e.g. brp = 000010b tseg1 = 0101b tseg2 = 010b tseg2 tseg1 sample point(s) nominal bit time t clk baud rate prescaler fig.12 general structure of a bit period.
2000 jul 26 42 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.10 rx m essage c ounter (rmc) the rmc register (can address 9) reflects the number of messages available within the rxfifo. the value is incremented with each receive event and decremented by the release receive buffer command. after any reset event, this register is cleared. table 22 rx message counter (rmc) (can address 9) 7 6 5 4 3 2 1 0 rmc.7 rmc.6 rmc.5 rmc.4 rmc.3 rmc.2 rmc.1 rmc.0 12.5.11 rx b uffer s ta rt a ddress (rbsa) the rbsa register (can address 10) reflects the currently valid internal ram address, where the first byte of the received message, which is mapped to the receive buffer window, is stored. with the help of this information it is possible to interpret the internal ram contents. the internal ram address area begins at can address 32 and may be accessed by the cpu for reading and writing (writing in reset mode only). example: if rbsa is set to 24 (decimal), the current message visible in the receive buffer window (can address 96 -108) is stored within the internal ram beginning at ram address 24. because the ram is also mapped directly to the can address space beginning at can address 128 (equal to ram address 0) this message may also be accessed using can address 152 and the following bytes (can address = rbsa + 128--> 24 + 128= 152). always, the release receive buffer command is given while there is at least one more message available within the fifo, rbsa is updated to the beginning of the next message. on hardware reset, this pointer is initialised to ?0h? upon a software reset (setting of reset mode) this pointer keeps its old value, but the fifo is cleared, what means, that the ram contents are not changed, but the next received (or transmitted) message will override the currently visible message within the receive buffer window. the rx buffer start address register appears to the cpu as a read only memory in operating mode and as read / write memory in reset mode. table 23 rx buffer start address (rbsa) (can address 10) 7 6 5 4 3 2 1 0 rbsa.7 rbsa.6 rbsa.5 rbsa.4 rbsa.3 rbsa.2 rbsa.1 rbsa.0
2000 jul 26 43 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.12 a rbitration l ost c apture (alc) this register contains information about the bit position of losing arbitration. the arbitration lost capture register appears to the cpu as a read only memory. reserved bits are read as ?? table 24 arbitration lost capture (alc) (can address 11) table 25 description of arbitration lost capture (alc) register bits on arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. in the same time, the current bit position of the bit stream processor is captured into the arbitration lost capture register. the content within this register is fixed until the users software has read out its contents once. from now on the capture mechanism is activated again. the corresponding interrupt flag located in the interrupt register is cleared during the read access to the interrupt register. a new arbitration lost interrupt is not possible until the arbitration lost capture register is read out once. 7 6 5 4 3 2 1 0 - - - bitno4 bitno3 bitno2 bitno1 bitno0 bit symbol name value function 7 to 5 ?? ? reserved. 4 bitno4 bit number 4 binary coded frame bit number where arbitration was lost. 00 -> arbitration lost in ?st bit of identi?r 3 bitno3 bit number 3 2 bitno2 bit number 2 11 -> arbitration lost in srtr bit (rtr bit for standard frame messages) 12 -> arbitration lost in ide bit 13 -> arbitration lost in 12th bit of identi?r (extended frame only) 1 bitno1 bit number 1 0 bitno0 bit number 0 30 -> arbitration lost in last bit of identi?r (extended frame only) 31 -> arbitration lost in rtr bit (extended frame only) width mhi013 id28 arbitration lost alc = 08 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 srtr ide id17 id16 id15 id14 id13 id12 id11 id10 id09 id08 id07 id06 id05 00 bit number: standard and extended frame messages: extended frame messages: example: tx rx 01 02 03 04 05 06 07 08 09 10 11 12 13 bit number: 14 15 16 17 18 19 20 21 22 bit number: 00 01 02 03 04 05 06 07 08 23 24 25 id04 26 id03 27 id02 28 id01 29 id00 30 rtr 31 start of frame fig.13 arbitration lost bit number interpretation.
2000 jul 26 44 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.13 e rror c ode c apture (ecc) this register contains information about the type and location of errors on the bus. the error code capture register appears to the cpu as a read only memory. table 26 error code capture (ecc) (can address 12) table 27 description of error code capture (ecc) register bits 7 6 5 4 3 2 1 0 errc1 errc0 dir seg4 seg3 seg2 seg1 seg0 bit symbol name value function 7 errc1 error code 1 errc1 errc0 6 errc0 error code 0 0 0 1 1 0 1 0 1 bit error form error stuff error other error 5 dir direction 1 (rx) 0 (tx) error occurred during reception error occurred during transmission 4 seg4 segment 4 re?cts the current frame segment to determine between different error events: 3 seg3 segment 3 00011 start of frame 2 seg2 segment 2 00010 id28 ... id21 1 seg1 segment 1 00110 id20 ... id18 0 seg0 segment 0 00100 00101 00111 01111 01110 01100 01101 01001 01011 01010 01000 11000 11001 11011 11010 10010 10001 10110 10011 10111 11100 srtr bit ide bit id17 ... id13 id12 ... id5 id4 ... id0 rtr bit reserved bit 1 reserved bit 0 data length code data field crc sequence crc delimiter acknowledge slot acknowledge delimiter end of frame intermission active error flag passive error flag tolerate dom. bits error delimiter overload flag
2000 jul 26 45 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 always if a bus error occurs, the corresponding bus error interrupt is forced, if enabled. in the same time, the current position of the bit stream processor is captured into the error code capture register. the content within this register is fixed until the users software has read out its content once. from now on the capture mechanism is activated again. the corresponding interrupt flag located in the interrupt register is cleared during the read access to the interrupt register. a new bus error interrupt is not possible until the capture register is read out once. 12.5.14 e rror w arning l imit r egister (ewlr) the error warning limit could be defined within this register. the default value (after hardware reset) is 96d. in reset mode this register appears to the cpu as a read / write memory. table 28 error warning limit register (ewlr) (can address 13) note that a content change of the ewl-register is possible only, if the reset mode was entered previously. an error status change (status register) and an error warning interrupt forced by the new register content will not occur, until the reset mode is cancelled again. 12.5.15 rx e rror c ounter r egister (rxerr) the rx error counter register reflects the current value of the receive error counter. after hardware reset this register is initialised to ?? in operating mode this register appears to the cpu as a read only memory. a write access to this register is possible only in reset mode. if a bus off event occurs, the rx error counter is initialised to ?? as long as bus off is valid, writing to this register has no effect. table 29 rx error counter register (rxerr) (can address 14) note that a cpu-forced content change of the rx error counter is possible only, if the reset mode was entered previously. an error status change (status register), an error warning or an error passive interrupt forced by the new register content will not occur, until the reset mode is cancelled again. 7 6 5 4 3 2 1 0 ewl.7 ewl.6 ewl.5 ewl.4 ewl.3 ewl.2 ewl.1 ewl.0 7 6 5 4 3 2 1 0 rxerr.7 rxerr.6 rxerr.5 rxerr.4 rxerr.3 rxerr.2 rxerr.1 rxerr.0
2000 jul 26 46 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.16 tx e rror c ounter r egister (txerr) the tx error counter register reflects the current value of the transmit error counter. in operating mode this register appears to the cpu as a read only memory. a write access to this register is possible only in reset mode. after hardware reset this register is initialised to ?? if a bus-off event occurs, the tx error counter is initialised to 127 to count the minimum protocol-defined time (128 occurrences of the bus-free signal). reading the tx error counter during this time gives information about the status of the bus-off recovery. if bus off is active, a write access to txerr in the range of 0 to 254 clears the bus off flag and the controller will wait for one occurrence of 11 consecutive recessive bits (bus free) after clearing of reset mode. writing 255 to txerr allows to initiate a cpu-driven bus off event. note, that a cpu-forced content change of the tx error counter is possible only, if the reset mode was entered previously. an error or bus status change (status register), an error warning or an error passive interrupt forced by the new register content will not occur, until the reset mode is cancelled again. after leaving the reset mode, the new tx counter content is interpreted and the bus off event is performed in the same way, as if it was forced by a bus error event. that means, that the reset mode is entered again, the tx error counter is initialised to 127, the rx counter is cleared and all concerned status and interrupt register bits are set. clearing of reset mode now will perform the protocol defined bus off recovery sequence (waiting for 128 occurrences of the bus-free signal). if the reset mode is entered again before the end of bus off recovery (txerr > 0), bus off keeps active and txerr is frozen. table 30 tx error counter register (txerr) (can address 15) 7 6 5 4 3 2 1 0 txerr.7 txerr.6 txerr.5 txerr.4 txerr.3 txerr.2 txerr.1 txerr.0 12.5.17 a cceptance f ilter with the help of the acceptance filter the can controller is able to allow passing of received messages to the rxfifo only when the identifier bits and the frame type of the received message are equal to the predefined ones within the acceptance filter registers. if at least one filter matches, the message is copied to the receive fifo. the acceptance filter is defined by the acceptance code registers (acrn) and the acceptance mask registers (amrn). within the acceptance code registers the bit patterns of messages to be received are defined. the corresponding acceptance mask registers allow defining certain bit positions to be ?on? care? the pelican is designed to support four of so called acceptance filter banks. each bank has the functionality known from the sja1000 with the extension, that a filter change is possible ?n the fly? additionally the used frame format of each filter bank is programmable now.
2000 jul 26 47 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.14 acceptance filter banks. handbook, full pagewidth mhi014 acceptance filter bank 4 acr 0 mformatb4 amodeb4 mformatb3 amodeb3 mformatb2 acceptance filter mode register amodeb2 mformatb1 amodeb1 b4f2en b4f1en b3f2en b3f1en b2f2en acceptance filter enable register b2f1en b1f2en b1f1en dual/single standard/ extended acr 1 acr 2 acr 3 amr 0 amr 1 amr 2 amr 3 acceptance filter bank 3 acr 0 acr 1 acr 2 acr 3 amr 0 amr 1 amr 2 amr 3 acceptance filter bank 2 acr 0 acr 1 acr 2 acr 3 amr 0 amr 1 amr 2 amr 3 acceptance filter bank 1 acr 0 acr 1 acr 2 acr 3 amr 0 amr 1 amr 2 amr 3 dual/single standard/ extended dual/single standard/ extended dual/single standard/ extended filter 2 enable/ disable filter 2 enable/ disable filter 1 enable/ disable filter 1 enable/ disable filter 2 enable/ disable filter 1 enable/ disable filter 2 enable/ disable filter 1 enable/ disable b4f2prio b4f1prio b3f2prio b3f1prio b2f2prio acceptance filter priority register b2f1prio b1f2prio b1f1prio filter 2 priority low/high filter 2 priority low/high filter 1 priority low/high filter 1 priority low/high filter 2 priority low/high filter 1 priority low/high filter 2 priority low/high filter 1 priority low/high
2000 jul 26 48 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.17.1 acceptance filter mode register the current operating mode is defined within the acceptance filter mode register located at can address 29. a write access to this register is possible only within reset mode (mode register). table 31 acceptance filter mode register (acf mode) (can address 29) 7 6 5 4 3 2 1 0 mformatb4 amodeb4 mformatb3 amodeb3 mformatb2 amodeb2 mformatb1 amodeb1 table 32 acceptance filter mode register (acf mode) 1 bits bit symbol name value function acfmod.7 mformatb4 acceptance filter format bank 4 1 (eff) acceptance filter bank 4 is used for extended frame messages only, standard frame messages are ignored 0 (sff) acceptance filter bank 4 is used for standard frame messages only, extended frame messages are ignored acfmod.6 amodeb4 acceptance filter mode bank 4 1 (single) the single acceptance filter option is enabled for ?ter bank 4, -> one long ?ter is active 0 (dual) the dual acceptance filter option is enabled for ?ter bank 4, -> two short ?ters are active acfmod.5 mformatb3 acceptance filter format bank 3 1 (eff) acceptance filter bank 3 is used for extended frame messages only, standard frame messages are ignored 0 (sff) acceptance filter bank 3 is used for standard frame messages only, extended frame messages are ignored acfmod..4 amodeb3 acceptance filter mode bank 3 1 (single) the single acceptance filter option is enabled for ?ter bank 3, -> one long ?ter is active 0 (dual) the dual acceptance filter option is enabled for ?ter bank 3, -> two short ?ters are active acfmod.3 mformatb2 acceptance filter format bank 2 1 (eff) acceptance filter bank 2 is used for extended frame messages only, standard frame messages are ignored. 0 (sff) acceptance filter bank 2 is used for standard frame messages only, extended frame messages are ignored. acfmod.2 amodeb2 acceptance filter mode bank 2 1 (single) the single acceptance filter option is enabled for ?ter bank 2, -> one long ?ter is active 0 (dual) the dual acceptance filter option is enabled for ?ter bank 2, -> two short ?ters are active acfmod.1 mformatb1 acceptance filter format bank 1 1 (eff) acceptance filter bank 1 is used for extended frame messages only, standard frame messages are ignored 0 (sff) acceptance filter bank 1 is used for standard frame messages only, extended frame messages are ignored acfmod.0 amodeb1 acceptance filter mode bank 1 1 (single) the single acceptance filter option is enabled for ?ter bank 1, -> one long ?ter is active 0 (dual) the dual acceptance filter option is enabled for ?ter bank 1, -> two short ?ters are active
2000 jul 26 49 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.17.2 acceptance filter enable register each defined acceptance filter is enabled or disabled by a certain bit located within the acceptance filter enable register. this allows to change the acceptance filter contents ?n the fly during normal operation if the corresponding filter is disabled previously. a disabled acceptance filter does not allow passing of messages to the receive buffer. if all acceptance filters are disabled (default after hardware reset) no messages will pass to the receive buffer at all. table 33 acceptance filter enable register (acf enable) (can address 30) 7 6 5 4 3 2 1 0 b4f2en b4f1en b3f2en b3f1en b2f2en b2f1en b1f2en b1f1en table 34 acceptance filter enable register (acf enable) note, if the single filter mode is selected for an acceptance filter bank, this single filter is related to the corresponding filter 1 enable bit. the filter 2 enable bits have no influence within single filter mode. bit symbol name value function acfen.7 b4f2en bank 4 filter 2 enable 1 (enabled) filter 2 of bank 4 is enabled, no write access to corresponding mask and code registers is possible 0 (disabled) filter 2 of bank 4 is disabled, changing of corresponding mask and code registers is possible. acfen.6 b4f1en bank 4 filter 1 enable 1 (enabled) filter 1 of bank 4 is enabled, no write access to corresponding mask and code registers is possible 0 (disabled) filter 1 of bank 4 is disabled, changing of corresponding mask and code registers is possible. acfen.5 b3f2en bank 3 filter 2 enable 1 (enabled) filter 2 of bank 3 is enabled, no write access to corresponding mask and code registers is possible 0 (disabled) filter 2 of bank 3 is disabled, changing of corresponding mask and code registers is possible. acfen.4 b3f1en bank 3 filter 1 enable 1 (enabled) filter 1 of bank 3 is enabled, no write access to corresponding mask and code registers is possible 0 (disabled) filter 1 of bank 3 is disabled, changing of corresponding mask and code registers is possible. acfen.3 b2f2en bank 2 filter 2 enable 1 (enabled) filter 2 of bank 2 is enabled, no write access to corresponding mask and code registers is possible 0 (disabled) filter 2 of bank 2 is disabled, changing of corresponding mask and code registers is possible. acfen.2 b2f1en bank 2 filter 1 enable 1 (enabled) filter 1 of bank 2 is enabled, no write access to corresponding mask and code registers is possible 0 (disabled) filter 1 of bank 2 is disabled, changing of corresponding mask and code registers is possible. acfen.1 b1f2en bank 1 filter 2 enable 1 (enabled) filter 2 of bank 1 is enabled, no write access to corresponding mask and code registers is possible 0 (disabled) filter 2 of bank 1 is disabled, changing of corresponding mask and code registers is possible. acfen.0 b1f1en bank 1 filter 1 enable 1 (enabled) filter 1 of bank 1 is enabled, no write access to corresponding mask and code registers is possible 0 (disabled) filter 1 of bank 1 is disabled, changing of corresponding mask and code registers is possible.
2000 jul 26 50 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.17.3 acceptance filter priority register for each available acceptance filter it could be defined, whether a receive interrupt is forced immediately if a message passes a certain acceptance filter or whether the programmed receive interrupt level should be used for interruption. this allows to use certain acceptance filters for alarm message recognition interrupting the host cpu immediately. table 35 acceptance filter priority register (acf priority) (can address 31) 7 6 5 4 3 2 1 0 b4f2prio b4f1prio b3f2prio b3f1prio b2f2prio b2f1prio b1f2prio b1f1prio table 36 acceptance filter priority register (acf priority) bit symbol name value function acfprio.7 b4f2prio bank 4 filter 2 priority 1 (high) a receive interrupt is generated immediately, if a message passes filter 2 within acceptance filter bank 4 0 (low) a receive interrupt is generated, if the fifo level exceeds the receive interrupt level register. acfprio.6 b4f1prio bank 4 filter 1 priority 1 (high) a receive interrupt is generated immediately, if a message passes filter 1 within acceptance filter bank 4 0 (low) a receive interrupt is generated, if the fifo level exceeds the receive interrupt level register. acfprio.5 b3f2prio bank 3 filter 2 priority 1 (high) a receive interrupt is generated immediately, if a message passes filter 2 within acceptance filter bank 3 0 (low) a receive interrupt is generated, if the fifo level exceeds the receive interrupt level register. acfprio.4 b3f1prio bank 3 filter 1 priority 1 (high) a receive interrupt is generated immediately, if a message passes filter 1 within acceptance filter bank 3 0 (low) a receive interrupt is generated, if the fifo level exceeds the receive interrupt level register. acfprio.3 b2f2prio bank 2filter 2 priority 1 (high) a receive interrupt is generated immediately, if a message passes filter 2 within acceptance filter bank 2 0 (low) a receive interrupt is generated, if the fifo level exceeds the receive interrupt level register. acfprio.2 b2f1prio bank 2 filter 1 priority 1 (high) a receive interrupt is generated immediately, if a message passes filter 1 within acceptance filter bank 2 0 (low) a receive interrupt is generated, if the fifo level exceeds the receive interrupt level register. acfprio.1 b1f2prio bank 1 filter 2 priority 1 (high) a receive interrupt is generated immediately, if a message passes filter 2 within acceptance filter bank 1 0 (low) a receive interrupt is generated, if the fifo level exceeds the receive interrupt level register. acfprio.0 b1f1prio bank 1 filter 1 priority 1 (high) a receive interrupt is generated immediately, if a message passes filter 1 within acceptance filter bank 1 0 (low) a receive interrupt is generated, if the fifo level exceeds the receive interrupt level register.
2000 jul 26 51 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.17.4 single filter con?uration in this filter configuration one long filter (4-byte) could be defined. the bit correspondences between the filter bytes and the message bytes depends on the programmed frame format (see acf mode register). single filter standard frame: if the standard frame format is selected, the complete identifier including the rtr bit and the first two data bytes are used for acceptance filtering. messages may also be accepted if there are no data bytes existing due to a set rtr bit or if there is no or only one data byte because of the corresponding data length code. for a successful reception of a message, all single bit comparisons have to signal acceptance. note that the 4 least significant bits of amr1 and acr1 are not used. in order to keep compatible with future products these bits should be programmed to be ?on? care?by setting amr1.3, amr1.2, amr1.1 and amr1.0 to ?? fig.15 single filter configuration, receiving standard frame messages. handbook, full pagewidth addr.: 16 acr0 7 6 5 4 3 2 10 msb lsb addr.: 18 acr2 7 6 5 4 3 2 10 msb lsb addr.: 19 acr3 7 6 5 4 3 2 10 msb lsb addr.: 17 acr1 7 6 5 4 3 2 10 msb lsb unused addr.: 20 amr0 7 6 5 4 3 2 10 id.28 id.27 id.26 id.25 id.24 id.23 id.22 msb lsb addr.: 22 amr2 7 6 5 4 3 2 10 msb lsb addr.: 23 amr3 7 6 5 4 3 2 10 msb lsb addr.: 21 amr1 7 6 5 4 3 2 10 msb lsb unused id.21 db1.7 db1.6 db1.5 db1.4 db1.3 db1.2 db1.1 db1.0 db2.7 db2.6 db2.5 db2.4 db2.3 db2.2 db2.1 db2.0 id.20 id.19 id.18 rtr & [6] [7] 0 1 not accepted accepted 1 [0] = message bit acceptance code bit acceptance mask bit dbx.y = data byte x, bit y mhi015
2000 jul 26 52 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 single filter extended frame: if the extended frame format is selected, the complete identifier including the rtr bit is used for acceptance filtering. for a successful reception of a message, all single bit comparisons have to signal acceptance. note that the 2 least significant bits of amr3 and acr3 are not used. in order to keep compatible with future products these bits should be programmed to be ?on? care?by setting amr3.1 and amr3.0 to ?? fig.16 single filter configuration, receiving extended frame messages. handbook, full pagewidth addr.: 16 acr0 7 6 5 4 3 2 10 msb lsb addr.: 18 acr2 7 6 5 4 3 2 10 msb lsb addr.: 19 acr3 7 6 5 4 3 2 10 msb lsb addr.: 17 acr1 7 6 5 4 3 2 10 msb lsb unused addr.: 20 amr0 7 6 5 4 3 2 10 id.28 id.27 id.26 id.25 id.24 id.23 id.22 msb lsb addr.: 22 amr2 7 6 5 4 3 2 10 msb lsb addr.: 23 amr3 7 6 5 4 3 2 10 msb lsb addr.: 21 amr1 7 6 5 4 3 2 10 msb lsb unused id.21 id.20 id.19 id.18 id.17 id.16 id.15 id.14 id.13 id.12 id.11 id.10 id.9 id.8 id.7 id.6 id.5 id.2 id.3 id.4 id.1 id.0 rtr & [6] [7] 0 1 not accepted accepted 1 [0] = message bit acceptance code bit acceptance mask bit mhi016
2000 jul 26 53 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.17.5 dual filter con?uration in this filter configuration two short filters could be defined. a received message is compared with both filters to decide, whether this message should be copied into the receive buffer or not. if at least one of the filters signals an acceptance, the received message becomes valid. the bit correspondences between the filter bytes and the message bytes depends on the currently received frame format. dual filter standard frame: if the standard frame format is selected, the two defined filters are different. the first filter compares the complete standard identifier including the rtr bit and the first data byte of the message. the second filter just compares the complete standard identifier including the rtr bit. fig.17 dual filter configuration, receiving standard frame messages. handbook, full pagewidth addr.: 16 acr0 7 6 5 4 3 2 10 msb lsb acr1 3 2 10 lsb acr3 3 2 10 lsb addr.: 17 7 6 54 msb id.28 id.27 id.26 id.25 id.24 id.23 id.22 id.21 id.20 id.19 id.18 rtr db1.7 db1.6 db1.5 db1.4 db1.1 db1.2 db1.3 db1.0 addr.: 20 amr0 7 6 5 4 3 2 10 msb lsb amr1 3 2 10 lsb amr3 3 2 10 lsb addr.: 21 7 6 54 msb [6] [7] 1 1 [0] [0] 1 = acceptance code bit acceptance mask bit filter 1 filter 2 filter 1 filter 2 message addr.: 22 amr2 7 6 5 4 3 2 10 msb lsb addr.: 23 amr3 7 6 5 4 msb addr.: 18 acr2 7 6 5 4 3 2 10 msb lsb addr.: 19 acr3 7 6 5 4 msb . . . . . . . . . . . . [6] [7] 0 1 not accepted accepted = message bit acceptance code bit acceptance mask bit . . . . . . . . . . . . & & mhi017
2000 jul 26 54 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 for a successful reception of a message, all single bit comparisons of at least one complete filter have to signal acceptance. in case of a set rtr bit or a data length code of ??no data byte is existing. nevertheless, a message may pass filter 1, if the first part up to the rtr bit signals acceptance. if no data byte filtering is required for filter 1, the four least significant bits of amr1 and amr3 have to be set ? (don? care). then both filters are working identically using the standard identifier range including the rtr bit. dual filter extended frame: if the extended frame format is selected, the two defined filters are looking identically. both filters are comparing the first two bytes of the extended identifier range only. for a successful reception of a message, all single bit comparisons of at least one complete filter have to signal acceptance. fig.18 dual filter configuration, receiving extended frame messages. handbook, full pagewidth addr.: 16 acr0 7 6 5 4 3 2 10 msb lsb id.28 id.27 id.26 id.25 id.24 id.23 id.22 id.21 id.20 id.19 id.18 id.17 id.16 id.15 id.14 id.13 addr.: 20 amr0 7 6 5 4 3 2 10 msb lsb [6] [7] 1 1 [0] [0] 1 = acceptance code bit acceptance mask bit filter 1 filter 2 filter 1 filter 2 message addr.: 22 amr2 7 6 5 4 3 2 10 msb lsb addr.: 23 amr3 addr.: 18 acr2 7 6 5 4 3 2 10 76543210 76543210 msb lsb msb lsb msb lsb addr.: 19 acr3 . . . . . . . . . . . . [6] [7] 0 1 not accepted accepted = message bit acceptance code bit acceptance mask bit . . . . . . . . . . . . & & mhi018 addr.: 17 acr1 6 7 5 4 3 2 10 msb lsb addr.: 21 amr1 6 7 5 4 3 2 10 msb lsb
2000 jul 26 55 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.18 t ransmit b uffer the global layout of the transmit buffer is shown in fig.19. one has to distinguish between the standard frame format (sff) and the extended frame format (eff) configuration. the transmit buffer allows the definition of one transmit message with up to eight data bytes. 12.5.18.1 transmit buffer layout it is subdivided into descriptor and data field where the first byte of the descriptor field is the frame information byte (frame info). it describes the frame format (sff or eff), remote or data frame and the data length. two identifier bytes for sff and four bytes for eff messages follow. the data field contains up to eight data bytes. the transmit buffer has a length of 13 bytes and is located in the can address range from 112 to 124. fig.19 transmit buffer layout for standard and extended frame format configurations. handbook, full pagewidth mhi023 tx frame information standard frame format (sff) 112 can address tx identifier 1 113 tx identifier 2 114 tx data byte 1 115 tx data byte 2 116 tx data byte 3 117 tx data byte 4 118 tx data byte 5 119 tx data byte 6 120 tx data byte 7 121 tx data byte 8 122 unused 123 unused 124 tx frame information extended frame format (eff) 112 can address tx identifier 1 113 tx identifier 2 114 tx identifier 3 115 tx identifier 4 116 tx data byte 1 117 tx data byte 2 118 tx data byte 3 119 tx data byte 4 120 tx data byte 5 121 tx data byte 6 122 tx data byte 7 123 tx data byte 8 124
2000 jul 26 56 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.18.2 descriptor field of the transmit buffer this configuration is chosen to be compatible with the receive buffer layout (see section 12.5.19.1). the values marked with ? ) in the transmit buffer should be set to the values expected in the receive buffer for an easy comparison, only when using the self reception facility, otherwise they are don? care. table 37 frame format (ff) and remote transmission request (rtr) bits bit value function ff 1 (eff) extended frame format will be transmitted by the can controller 0 (sff) standard frame format will be transmitted by the can controller rtr 1 (remote) remote frame will be transmitted by the can controller 0 (data) data frame will be transmitted by the can controller fig.20 bit layout transmit buffer. 7 ff 6 rtr 5 (0) 4 (0) 3 dlc.3 2 dlc.2 1 dlc.1 0 dlc.0 6 rtr 5 (0) 4 (0) 3 dlc.3 2 dlc.2 1 dlc.1 0 dlc.0 addr. 112 tx frame information addr. 112 tx frame information standard frame format (sff) extended frame format (eff) 7 id.28 6 id.27 5 id.26 4 id.25 3 id.24 2 id.23 1 id.22 0 id.21 addr 113 tx identi?r 1 7 id.20 6 id.19 5 id.18 4 (rtr) 3 (0) 2 (0) 1 (0) 0 (0) addr. 114 tx identi?r 2 7 id.28 6 id.27 5 id.26 4 id.25 3 id.24 2 id.23 1 id.22 0 id.21 addr. 113 tx identi?r 1 7 id.20 6 id.19 5 id.18 4 id.17 3 id.16 2 id.15 1 id.14 0 id.13 addr. 114 tx identi?r 2 7 id.12 6 id.11 5 id.10 4 id.9 3 id.8 2 id.7 1 id.6 0 id.5 addr. 115 tx identi?r 3 7 id.4 6 id.3 5 id.2 4 id.1 3 id.0 2 (rtr) 1 (0) 0 (0) addr. 116 tx identi?r 4 meaning of the transmit buffer bits: id.x identifier bit x ff frame format rtr remote transmission request dlc.x data length code bit x x don? care (0) don? care, but recommended to be compatible to receive buffer 7 ff
2000 jul 26 57 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.18.3 data length code (dlc) the number of bytes in the data field of a message is coded by the data length code. at the start of a remote frame transmission the data length code is not considered due to the rtr bit being ??(remote). this forces the number of transmitted/received data bytes to be 0. nevertheless, the data length code must be specified correctly to avoid bus errors, if two can controllers start a remote frame transmission with the same identifier simultaneously. the range of the data byte count is 0 to 8 bytes and is coded as follows: ` for reasons of compatibility no data length code > 8 should be used. if a value greater than 8 is selected, 8 bytes are transmitted in the data frame with the data length code specified in dlc. 12.5.18.4 identi?r (id) in standard frame format (sff) the identifier consists of 11 bits (id.28 to id.18) and in extended frame format (eff) messages the identifier consists of 29 bits (id.28 to id.0). id.28 is the most significant bit, which is transmitted first on the bus during the arbitration process. the identifier acts as the message? name, used in a receiver for acceptance filtering, and also determines the bus access priority during the arbitration process. the lower the binary value of the identifier the higher the priority. this is due to the larger number of leading dominant bits during arbitration. 12.5.18.5 data field the number of transferred data bytes is defined by the data length code. the first bit transmitted is the most significant bit of data byte 1 at address 115 (sff) or address 117 (eff). databytecount 8 dlc.3 4 dlc.2 2 dlc.1 dlc.0 + + + =
2000 jul 26 58 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.19 r eceive b uffer the global layout of the receive buffer is very similar to the transmit buffer described in the previous chapter. the receive buffer is the accessible part of the rxfifo and is located in the range between can address 96 and 108. each message is subdivided into a descriptor and a data field. fig.21 example of the message storage within the rxfifo. message 1 is now available in the receive buffer note that message 2 should not be read until it has been shifted to address 96 by a release receive buffer command because this message may be in process now and due to this not fixed. handbook, full pagewidth mhi019 message 3 message 2 message 1 receive buffer window incoming messages receive fifo 106 107 108 103 104 105 100 101 102 99 96 97 98
2000 jul 26 59 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 12.5.19.1 descriptor file of the receive buffer identifier, frame format, remote transmission request bit and data length code have the same meaning as described in the transmit buffer. fig.22 bit layout receive buffer. 7 id.28 6 id.27 5 id.26 4 id.25 3 id.24 2 id.23 1 id.22 0 id.21 7 id.28 6 id.27 5 id.26 4 id.25 3 id.24 2 id.23 1 id.22 0 id.21 addr. 97 rx identi?r 1 addr. 97 rx identi?r 1 standard frame format (sff) extended frame format (eff) 7 id.20 6 id.19 5 id.18 4 rtr 3 0 2 0 1 0 0 0 addr. 98 rx identi?r 2 7 id.20 6 id.19 5 id.18 4 id.17 3 id.16 2 id.15 1 id.14 0 id.13 addr. 98 rx identi?r 2 7 id.12 6 id.11 5 id.10 4 id.9 3 id.8 2 id.7 1 id.6 0 id.5 addr. 99 rx identi?r 3 7 id.4 6 id.3 5 id.2 4 id.1 3 id.0 2 rtr 1 0 0 0 addr. 100 rx identi?r 4 meaning of the receive buffer bits: id.x identifier bit x ff frame format rtr remote transmission request dlc.x data length code bit x 7 ff 6 rtr 5 0 4 0 3 dlc.3 2 dlc.2 1 dlc.1 0 dlc.0 addr. 96 rx frame information 7 ff 6 rtr 5 0 4 0 3 dlc.3 2 dlc.2 1 dlc.1 0 dlc.0 addr. 96 rx frame information note: the received data length code located in the frame information byte represents the real sent data length code, which may be greater than 8 (depends on transmitting can node). nevertheless, the maximum number of received data bytes is 8. this should be taken into account by reading a message from the receive buffer. it depends on the data length how many can messages can fit in the rxfifo at one time. if there is not enough space for a new message within the rxfifo, the can controller generates a data overrun condition the moment this message becomes valid and the acceptance test was positive. a message that is partly written into the rxfifo, when the data overrun situation occurs, is deleted. this situation is signalled to the cpu via the status register and the data overrun interrupt, if enabled.
2000 jul 26 60 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 13 serial i/o the P8XC591 is equipped with three independent serial ports: can, sio0 and sio1. sio0 is a standard serial interface uart with enhanced functionality. in following there will be one section describing the standard uart functionality and an extra section for enhanced uart. sio1 accommodates the i 2 c bus. 14 sio0 standard serial interface uart the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still hasn? been read by the time reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at special function register transmit registers are both accessed at special function register s0buf. writing to s0buf loads the transmit register, and reading s0buf accesses a physically separate receive register. the serial port can operate in 4 modes (one synchronous mode, three asynchronous modes). the baud rate clock for the serial port is derived from the oscillator frequency (mode 0, 2) or generated either by timer 1 or by dedicated baud rate generator (mode 1, 3). mode 0 shift register (synchronous) mode: serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/ received (lsb first). the baud rate is fixed 1 ? 6 the oscillator frequency. mode 1 8-bit uart, variable baud rate: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2 9-bit uart, fixed baud rate: 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (1). on transmit, the 9 th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9 th data bit goes into rb8 in special function register scon, while the stop bit ignored. the baud rate is programmable to either 1 ? 16 or 1 ? 32 the oscillator frequency. mode 3 9-bit uart, variable baud rate: 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses s0buf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. 14.1 multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9 th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first send out an address byte which indentifies the target slave. an address byte differs from a data byte in that the 9 th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren? being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 14.2 serial port control register the serial port control and status register is the special function register scon, shown in table 38, 40 and 41. this register contains not only the mode selection bits, but also the 9 th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). s0buf is the receive and transmit buffer of serial interface. writing to s0buf loads the transmit register and initiates transmission. reading out s0buf accesses a physically separate receive register.
2000 jul 26 61 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 14.3 baud rate generation there are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. for clarification some terms regarding the difference between ?aud rate clock?and ?aud rate?should be mentioned. the serial interface requires a clock rate which is 16 times the baud rate for internal synchronization. therefore, the baud rate generators have to provide a ?aud rate clock?to the serial interface which - there divided by 16 - results in the actual ?aud rate? however, all formulas given in the following section already include the factor and calculate the final baud rate. further, the abbreviation f clk refers to the external clock frequency (oscillator or external input clock operation). the baud rate of the serial port is controlled by the two bits sps and smod1 which are located in the special function registers s0psh and pcon. in sfrs s0psh and s0psl the prescaler load value of the internal baud rate generator can be programmed (see table 38 to 43). 14.3.1 i nternal b aud r at e g enerator p rescaler s0psh, s0psl table 38 internal baud rate generator prescaler low register s0psl (address fah) prescaler load value table 39 description of s0psl bits table 40 internal baud rate generator prescaler high register s0psh (address fbh) prescaler higher nibble load value table 41 description of s0psh bits 14.3.2 pcon for the i nternal b aud r at e g enerator table 42 pcon (address 87h) prescaler load value table 43 description of smod1 and smod0 bits 76543210 prescaler load value bit symbol description 7 to 0 ? baud reload low value. lower 8 bits of the baud rate timer reload value. 76543210 sps ??? higher nibble load value bit symbol description 7 sps baud rate generator enable. when set, the baud rate of serial interface is derived from the dedicated baud rate generator. when cleared (default after reset), baud rate is derived from the timer 1 over?w rate. 6 to 4 ? reserved. 3 to 0 ? baud rate generator reload high value. upper four bits of the baud rate timer value. 76543210 smod1 smod0 (pof) (wle) (gf1) (gf0) (pd) (idl) bit symbol description 7 smod1 double baud rate. when set, the baud rate of serial interface is modes 1, 2, 3 is doubled. after reset this bit is cleared. 6 smod0 double baud rate. selects sm0/fe for scon.7 bit. 5 to 0 (pof) to (idl) description refer to section 11.3.5 ?ower control register (pcon)?
2000 jul 26 62 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 14.3.3 b aud r at e g eneration o verview o f o ptions depending on the programmed operating mode different paths are selected for the baud rate clock generation. figure 23 shows the dependencies of the serial port baud rate clock generation on the two control bits and from the mode which is selected in the special function register scon: fig.23 baud rate generation for the serial port. note: the switch con?uration shows the reset state. handbook, full pagewidth mhi024 baud rate generator baud rate clock 6 (s0psh s0psl) s0psh.7 (sps) timer 1 overflow f clk scon.7 scon.6 (sm0/fe) mode 1 mode 3 only one mode can be selected mode 2 mode 0 0 1 pcon.7 (smod1) 0 1 2
2000 jul 26 63 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 14.3.4 b aud r at e i n m ode 0 the baud rate in mode 0 is fixed to: 14.3.5 b aud r at e i n m ode 2 the baud rate in mode 2 depends on the value of bit smod1 in special function register pcon. if smod1 = 0 (which is the value after reset), the baud rate is 1 ? 32 of oscillator frequency. if smod1 = 1, the baud rate is 1 ? 16 of the oscillator frequency: 14.3.6 b aud r at e i n m ode 1 and 3 in these modes the baud rate is variable and can be generated alternatively by a baud rate generator or by timer 1. mode 0 baud rate oscillator frequency 6 ------------------------------------------------------- = mode 2 baud rate 2 smod1 32 -------------------- oscillator frequency = 14.3.7 u sing the i nternal b aud r at e g enerator in modes 1 and 3, the P8XC591 can use an internal baud rate generator for the serial port. to enable this feature, bit sps (bit 7 of special function register s0psh) must be set. bit smod1 (pcon.7) controls a divide-by-2 circuit which affect the input and output clock signal of the baud rate generator. after reset the divide-by-2 circuit is active and the resulting overflow output clock will be divided by 2. the input clock of the baud rate generator is f clk. the baud rate generator consists of its own free running upward counting 12-bit timer. on overflow of this timer (next count step after counter value fffh) there is an automatic 12-bit reload from the registers s0psl and s0psh. the lower 8 bits of the timer are reloaded from s0psl, while the upper four bits are reloaded from bit 0 to 3 of register s0psh. the baud rate timer is reloaded by writing to s0psh. fig.24 serial port input clock when using the baud rate generator. note: the switch con?uration shows the reset state. handbook, full pagewidth mhi025 baud rate clock baud rate f clk pcon.7 (smod1) 0 1 2 12 bit timer s0psh s0psl overflow input clock .3 .2 .1 .0
2000 jul 26 64 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 with the baud rate generator as clock source for the serial port in mode 1 and mode 3, the baud rate of can be determined as follows: mode 1, 3 baud rate = baud rate generator overflow rate = 2 12 - s0ps with s0ps = s0psh.3 - 0, s0psl.7 - 0. s0ps: baud rate generator prescaler load value table 47 lists baud rates and how they can be obtained from the internal baud rate generator. 14.3.8 u sing t imer 1 to g enerate b aud r ates in mode 1 and 3 of the serial port also timer 1 can be used for generating baud rates. then the baud rate is determined by the timer 1 overflow rate and the value of smod1 as follows: 2 smod1 osciillator frequency 32 (baud rate generator overflow rate) --------------------------------------------------------------------------------------------------------- the timer 1 interrupt is usually disabled in this application. timer 1 itself can be configured for either ?imer?or ?ounter?operation, and in any of its operating modes. in most typical applications, it is configured for ?imer operation in the auto-reload (high nibble of tmod = 0010b). in this case the baud rate is given by the formula: very low baud rates can be achieved with timer 1 if leaving the timer 1 interrupt enabled, configuring the timer to run as 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt for a 16-bit software reload. table 49 lists lower baud rates and how they can be obtained from timer 1. mode 1, 3 baud rate 2 smod1 32 -------------------- (timer 1 overflow rate) = mode1 3 baud rate = 2 smod1 oscillator frequency 32 6 256 th1 () () ------------------------------------------------------------------------------ - , table 44 serial port control register scon (address) table 45 description of s0psh and s0psl bits 76543210 sm0 sm1 sm2 ren tb8 rb8 ti ri bit symbol description 7 sm0 see table 46. 6 sm1 see table 46. 5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9 th data bit (rb8) is 0. in mode 1, if sm2 = 1 then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. 4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. 3 tb8 the 9 th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. 2 rb8 in modes 2 and 3, is the 9 th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. 1ti transmit interrupt ?g. set by hardware at the end of the 8 th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. 0ri receive interrupt ?g. set by hardware at the end of the 8 th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software.
2000 jul 26 65 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 46 serial port mode select table 47 internal baud rate timer generated baud rates table 48 timer 1 generated baud rates sm0 sm1 mode description baud rate 0 0 mode 0 shift register 1 ? 6 f clk 0 1 mode 1 8-bit uart variable 1 0 mode 2 9-bit uart 1 ? 32 or 1 ? 16 f clk 1 1 mode 3 9-bit uart variable baud rate (kbits/s) f clk (mhz) sps smod1 internal baud rate timer deviation % mode reload value 750 12 1 1 0 1/3 fffh 500 8 1 1 0 1/3 fffh 250 8 1 0 0 1/3 fffh 250 8 1 1 0 1/3 ffeh 57.6 12 1 1 0.16 1/3 ff3h 38.4 8 1 1 0.16 1/3 ff3h 19.2 12 1 1 0.16 1/3 fd9h 9.6 12 1 1 0.16 1/3 fb2h 4.8 12 1 1 0.16 1/3 f64h 2.4 12 1 1 0.16 1/3 ec8h 0.11 8 1 0 ? 0.01 1/3 71fh baud rate (kbits/s) f clk (mhz) sps smod1 internal baud rate timer deviation % mode reload value 110 12 0 0 0.03 1 fdc8h 110 4 0 1 ? 0.06 1 fe85h 110 4 0 0 0.21 2 43h
2000 jul 26 66 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 14.4 more about uart modes more about mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb first). the baud rate is fixed a 1 ? 6 the oscillator frequency. figure 25 shows a simplified functional diagram of the serial port in mode 0, and associated timing. transmission is initiated by any instruction that uses s0buf as a destination register. the ?rite to s0buf signal at s6p2 also loads a 1 into the 9 th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between ?rite to s0buf?and activation of send. send enables the output of the shift register to the alternate output function line of p3.0 and also enable shift clock to the alternate output function line of p3.1. shift clock is low during s3, s4, and s5 of every machine cycle, and high during s6, s1 and s2. at s6p2 of every machine cycle in which send is active, the contents of the transmit shift are shifted to the right one position. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9 th position, is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control block to do one last shift and then deactivate send and set t1. both of these actions occur at s1p1 of the 10 th machine cycle after ?rite to s0buf? reception is initiated by the condition ren = 1 and r1 = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates receive. receive enable shift clock to the alternate output function line of p3.1. shift clock makes transitions at s3p1 and s6p1 of every machine cycle. at s6p2 of every machine cycle. at s6p2 of every machine cycle in which receive is active, the contents of the receive shift register are shifted to the left one position. the value that comes in from the right is the value that was sampled at the p3.0 pin at s5p2 of the same machine cycle. as data bits come in from the right, 1s shift out to the left. when the 0 that was initially loaded into the weightiness position arrives at the left most position in the shift register, it flags the rx control block to do one last shift and load s0buf. at s1p1 of the 10 th machine cycle after the write to scon that cleared ri, receive is cleared as ri is set. more about mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the 80c51 the baud rate is determined by the timer 1 overflow rate. figure 25 shows a simplified functional diagram of the serial port in mode1, and associated timings for transmit receive. transmission is initiated by any instruction that uses s0buf as a destination register. the ?rite to s0buf signal also loads a1 into the 9 th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the ?rite to s0buf?signal.) the transmission begins with activation of send which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9 th position is just to the left of the msb, and all positions to the left of that contain zeros. the condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 10 th divide-by-16 rollover after ?rite to s0buf? reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1 ffh is written into the input shift register. resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16 ths . at the 7 th , 8 th , and 9 th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it shifted into the input shift register, and reception of the rest of the frame will proceed.
2000 jul 26 67 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the left most position in the shift register (which in mode 1 is a 9-bit register), it flags the rx control block to do one last shift, load s0buf and rb8, and set ri. the signal to load s0buf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. ri = 0, and 2. either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into s0buf, and ri is activated. at this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in rxd. more about modes 2 and 3 eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (1). on transmit, the 9 th data bit (tb8) can be assigned the values of 0 or 1. on receive, the 9 the data bit goes into rb8 in scon. the baud rate is programmable to either 1 ? 16 or 1 ? 32 the oscillator frequency in mode 2. mode 3 may have a variable baud rate generated from timer 1. figure 25 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9 th bit of the transmit shift register. transmission is initiated by any instruction that uses s0buf as a destination register. the ?rite to s0buf signal also loads tb8 into the 9 th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the ?rite to sub?signal). the transmission begins with activation of send, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a 1 (the stop bit) into the 9 th bit position of the shift register. thereafter, only zeros are clocked in. thus, as data bit shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 11 th divide-by-16 rollover after ?rite to subf? reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the 7 th , 8 th , and 9 th counter states of each bit time, the bit detector samples the value of r-d. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the left most position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx control block to do one last shift, load s0buf and rb8, and set ri. the signal to load s0buf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. ri = 0, and 2. either sm2 = 0, or the received 9 th data bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9 th data bit goes into rb8, and the first 8 data bits go into s0buf. one bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the rxd input.
2000 jul 26 68 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.25 serial port mode 0. handbook, full pagewidth sbuf tx control t1 start tx clock shift send s write to sbuf serial port interrupt s6 q d cl zero detector input shift register shift clock sbuf load sbuf read sbuf lsb msb lsb ren ri msb r1 rxd p3.0 alt input function txd p3.1 alt output function rxd p3.0 alt output function rx control 0 1 1 1 1 1 1 1 shift start rx clock shift receive mhi026 80c51 internal bus 80c51 internal bus s1 . . . . s6 s1 . . . . s6 s1 . . . . s6 s1 . . . . s6 s1 . . . . s6 s1 . . . . s6 s1 . . . . s6 s1 . . . . s6 s1 . . . . s6 s1 . . . . s6 s1 s4 . . ale shift shift send txd (shift clock) txd (shift clock) receive rxd (data out) rxd (data in) s3p1 s5p2 write to scon (clear ri) ti ri d0 write to sbuf s6p2 s6p1 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transmit receive
2000 jul 26 69 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.26 serial port mode 1. handbook, full pagewidth txd sbuf shift tx control t1 start tx clock data send s tb8 write to sbuf serial port interrupt baud rate clock sample q d cl zero detector 1-to-0 transition detector rxd bit detector input shift register (9 bits) sbuf load sbuf read sbuf r1 rx control 1ffh shift rx clock start load sbuf shift mhi027 d4 d5 d6 d3 d2 d1 d0 start bit 16 reset d7 stop bit d4 d5 d6 d3 d2 d1 d0 start bit d7 stop bit transmit receive tx clock write to sbuf send data shift txd ti rx clock rxd bit detector sample times shift ri s1p1 80c51 internal bus 80c51 internal bus 16 16
2000 jul 26 70 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.27 serial port mode 2 and 3. handbook, full pagewidth txd sbuf shift tx control t1 stop bit gen. start tx clock data send s tb8 write to sbuf serial port interrupt baud rate clock sample q d cl zero detector 1-to-0 transition detector rxd bit detector input shift register (9 bits) sbuf load sbuf read sbuf r1 rx control 1ffh shift rx clock start load sbuf shift mhi028 d4 d5 d6 d3 d2 d1 d0 start bit d7 tb8 stop bit d4 d5 d6 d3 d2 d1 d0 start bit d7 tb8 stop bit transmit receive tx clock write to sbuf send data shift txd ti stop bit gen. rx clock rxd bit detector sample times shift ri s1p1 80c51 internal bus 80c51 internal bus 16 reset 16 16
2000 jul 26 71 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 14.5 enhanced uart the uart operates in all of the usual modes that are described in the section of standard serial interface, 80c51-based 8-bit microcontrollers. in addition the uart can perform framing error detect by looking for missing stop bits, and automatic address recognition. the uart also fully supports multiprocessor communication as does the standard 80c51 uart. when used for framing error detect the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the s0con register. the fe bit shares the s0con.7 bit with sm0 and the function of s0con.7 is determined by pcon.6 (smod0) see table 50. if smod0 is set then s0con.7 functions as fe. s0con.7 functions as sm0 when smod0 is cleared. when as fe s0con.7 can only be cleared by software. refer to figure 25. 14.5.1 a utomatic a ddress r ecognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in s0con. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the ?iven?address or the ?roadcast address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 29. the 8 bit mode is called mode 1. in this mode the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. 14.5.2 s erial p ort c ontrol r egister (s0con) table 49 serial port control register (address 98h) table 50 description of s0con bits 76543210 sm0/fe sm1 sm2 ren tb8 rb8 ti ri bit symbol description 7fe sm0 framing error bit. this bit is set by the receiver when an invalid stop bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. serial port mode bit 0, (smod0 must = 0 to access bit sm0), see table 46. 6 sm1 these bits are used to select the serial port mode; see table 46. 5 sm2 enables the automatic address recognition feature in modes 2 and 3. if sm2 = 1, then ri will not be set unless the received 9 th data bit (rb8) is a logic 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1, then ri will not be activated unless a valid stop bit was not received, and the received byte is a given or broadcast address. in mode 0, sm2 should be a logic 0. 4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. 3 tb8 the 9 th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. 2 rb8 in modes 2 and 3, the 9 th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. 1ti transmit interrupt ?g . set by hardware at the end of the 8 th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. 0ri receive interrupt ?g . set by hardware at the end of the 8 th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software.
2000 jul 26 72 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.28 uart framing error detection. handbook, full pagewidth mhi029 sm0/fe sm1 sm2 ren tb8 rb8 ti ri smod1 smod0 0 : s0con.7 = sm0 1 : s0con.7 = fe pof wle gf1 gf0 pd idl scon (98h) pcon (87h) set fe bit if stop bit is 0 (framing error) sm0 to uart mode control d0 d1 d2 d3 d4 d5 d6 d7 d8 start bit data byte only in mode 2, 3 stop bit fig.29 uart multiprocessor communication, automatic address recognition. handbook, full pagewidth mhi030 sm0 sm1 sm2 ren tb8 11 11x 10 comparator rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren = 1, rb8 = 1 and ?eceived address?= ?rogrammed address when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address.
2000 jul 26 73 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 mode 0 is the shift register mode and sm2 is ignored. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave? address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are ?on? care? the saden mask can be logically anded with the saddr to create the ?iven?address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two salves. slave 0 requires as 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are trended as don? cares. in most cases, interpreting the don?-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr (sfr address 0a9h) and saden (sfr address 0b9h) are leaded with 0s. this produces a given address of all ?on? cares?as well as a broadcast address of all ?on? cares? this effectively disables the automatic addressing mode and allows the microcontroller to use standard 80c51 type uart drivers which do not make use of this feature. 15 sio1, i 2 c serial io the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: ? bidirectional data transfer between masters and slaves ? multimaster bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c bus may be used for test and diagnostic purposes the i/o pins p1.6 and p1.7 must be set to open drain (scl and sda). the 8xc591 on-chip i 2 c logic provides a serial interface that meets the i 2 c bus specification. the sio1 logic handles bytes transfer autonomously. it also keeps track of serial transfers, and a status register (s1sta) reflects the status of sio1 and the i 2 c bus.
2000 jul 26 74 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 the cpu interfaces to the i 2 c logic via the following four special function registers: s1con (sio1 control register), s1sta (sio1 status register), s1dat (sio1 data register), and s1adr (sio1 slave address register). the sio1 logic interfaces to the external i 2 c bus via two port 1 pins: p1.6/scl (serial clock line) and p1.7/sda (serial data line). a typical i 2 c bus configuration is shown in figure 30, and figure 31 shows how a data transfer is accomplished on the bus. depending on the state of the direction bit (r/w), two types of data transfers are possible on the i 2 c bus: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. 15.1 modes of operation the on-chip sio1 logic may operate in the following four modes: 1. master transmitter mode: serial data output through p1.7/sda while p1.6/scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. in this case the data direction bit (r/w) will be logic 0, and we say that a ? is transmitted. thus the first byte transmitted is sla+w. serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. 2. master receiver mode: the first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. in this case the data direction bit (r/w) will be logic 1, and we say that an ? is transmitted. thus the first byte transmitted is sla+r. serial data is received via p1.7/sda while p1.6/scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are output to indicate the beginning and end of a serial transfer. 3. slave receiver mode: serial data and the serial clock are received through p1.7/sda and p1.6/scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. 4. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted via p1.7/sda while the serial clock is input through p1.6/scl. start and stop conditions are recognized as the beginning and end of a serial transfer. in a given application, sio1 may operate as a master and as a slave. in the slave mode, the sio1 hardware looks for its own slave address and the general call address. if one of these addresses is detected, an interrupt is requested. when the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bus arbitration is lost in the master mode, sio1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer.
2000 jul 26 75 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.30 typical i 2 c bus configuration. handbook, full pagewidth mhi031 other device with i 2 c interface r p other device with i 2 c interface r p sda v dd scl p1.7/sda p1.6/scl 8xc591 i 2 c-bus fig.31 data transfer on the i 2 c bus. handbook, full pagewidth mhi032 slave address r/w direction bit acknowledgment signal from receiver repeated if more bytes are transferred clock line held low while interrupts are serviced acknowledgment signal from receiver msb 12 789 ack 1 2 3-8 9 ack sda scl stop condition start condition repeated start condition p/s s
2000 jul 26 76 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.2 sio1 implementation and operation figure 32 shows how the on-chip i 2 c bus interface is implemented, and the following text describes the individual blocks. 15.2.1 i nput f ilters and o utput s tages the input filters have i 2 c compatible input levels. if the input voltage is less than 1.5 v, the input logic level is interpreted as 0; if the input voltage is greater than 3.0 v, the input logic level is interpreted as 1. input signals are synchronized with the internal clock (f clk /4), and spikes shorter than three oscillator periods are filtered out. the output stages consist of open drain transistors that can sink 3 ma at v out < 0.4 v. these open drain outputs do have clamping diodes to v dd . thus, precautions have to be considered, if a powered-down 8xc591 on one board clamps the i 2 c bus externally. 15.2.2 a ddress r egister , s1adr this 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which sio1 will respond when programmed as a slave transmitter or receiver. the lsb (gc) is used to enable general call address (00h) recognition. 15.2.3 c omparator the comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in s1adr). it also compares the first received 8-bit byte with the general call address (00h). if an equality is found, the appropriate status bits are set and an interrupt is requested. 15.2.4 s hift r egister , s1dat this 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been received. data in s1dat is always shifted from right to left; the first bit to be transmitted is the msb (bit 7) and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat.
2000 jul 26 77 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.32 i 2 c bus interface block diagram. handbook, full pagewidth mhi033 8 8 8 8 address register comparator shift register control register ack timing & control logic input filter output stage input filter p1.7 output stage 1/4 f osc interrupt timer 1 overflow arbitration & sync logic status decoder serial clock generator s1adr s1dat status register s1sta status bits s1con p1.7/sda p1.6 p1.6/scl internal bus
2000 jul 26 78 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.2.5 a rbitration and s ynchronization l ogic in the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the i 2 c bus. if another device on the bus overrules a logic 1 and pulls the sda line low, arbitration is lost, and sio1 immediately changes from master transmitter to slave receiver. sio1 will continue to output clock pulses (on scl) until transmission of the current serial byte is complete. arbitration may also be lost in the master receiver mode. loss of arbitration in this mode can only occur while sio1 is returning a not acknowledge: (logic 1) to the bus. arbitration is lost when another device on the bus pulls this signal low. since this can occur only at the end of a serial byte, sio1 generates no further clock pulses. figure 33 shows the arbitration procedure. the synchronization logic will synchronize the serial clock generator with the clock pulses on the scl line from another device. if two or more master devices generate clock pulses, the mark duration is determined by the device that generates the shortest marks, and the space duration is determined by the device that generates the longest spaces. figure 34 shows the synchronization procedure. a slave may stretch the space duration to slow down the bus master. the space duration may also be stretched for handshaking purposes. this can be done after each bit or after a complete byte transfer. sio1 will stretch the scl space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. the serial interrupt flag (si) is set, and the stretching continues until the serial interrupt flag is cleared. fig.33 arbitration procedure. handbook, full pagewidth mhi034 sda scl 1234 89 ack (2) (1) (1) (3) (1) another device transmits identical serial data. (2) another device overrules a logic 1 (dotted line) transmitted by sio1 (master) by pulling the sda line low. arbitration is lo st, and sio1 enters the slave receiver mode. (3) sio1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. sio1 will not generate clock pulses for the next byte. data on sda originates from the new master once it has won arbitration.
2000 jul 26 79 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.34 serial clock synchronization. handbook, full pagewidth mhi035 sda scl (1) (3) (1) (2) mark duration space duration (1) another service pulls the scl line low before the sio ?ask duration is complete. the serial clock generator is immediately reset and commences with the ?pace?duration by pulling scl low. (2) another device still pulls the scl line low after sio1 releases scl. the serial clock generator is forced into the wait state until the scl line is released. (3) the scl line is released, and the serial clock generator commences with the mark duration. 15.2.6 s erial c lock g enerator this programmable clock pulse generator provides the scl clock pulses when sio1 is in the master transmitter or master receiver mode. it is switched off when sio1 is in a slave mode. the programmable output clock frequencies are: f clk /120, f clk /9600, and the timer 1 overflow rate divided by eight. the output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other scl clock sources as described above. 15.2.7 t iming and c ontrol the timing and control logic generates the timing and control signals for serial byte handling. this logic block provides the shift pulses for s1dat, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the i 2 c bus status. 15.2.8 c ontrol r egister , s1con this 7-bit special function register is used by the microcontroller to control the following sio1 functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. 15.2.9 s tatus d ecoder and s tatus r egister the status decoder takes all of the internal status bits and compresses them into a 5-bit code. this code is unique for each i 2 c bus status. the 5-bit code may be used to generate vector addresses for fast processing of the various service routines. each service routine processes a particular bus status. there are 26 possible bus states if all four modes of sio1 are used. the 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. the three least significant bits of the status register are always zero. if the status code is used as a vector to service routines, then the routines are displaced by eight address locations. eight bytes of code is sufficient for most of the service routines (see the software example in this section). 15.2.10 t he f our sio1 s pecial f unction r egisters the microcontroller interfaces to sio1 via four special function registers. these four sfrs (s1adr, s1dat, s1con, and s1sta) are described individually in the following sections.
2000 jul 26 80 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.2.10.1 the address register, s1adr the cpu can read from and write to this 8-bit, directly addressable sfr. s1adr is not affected by the sio1 hardware. the contents of this register are irrelevant when sio1 is in a master mode. in the slave modes, the seven most significant bits must be loaded with the microcontrollers own slave address, and, if the least significant bit is set, the general call address (00h) is recognized; otherwise it is ignored. the most significant bit corresponds to the first bit received from the i 2 c bus after a start condition. a logic 1 in s1adr corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. table 51 address register s1adr (address dbh) table 52 description of s1adr (dbh) bits 76543210 xxxxxxxgc bit symbol description 7 to 1 x own slave address. 0 gc 0 = general call address is not recognized. 1 = general call address is recognized. 15.2.11 t he d ata r egister , s1dat s1dat contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from and write to this 8-bit, directly addressable sfr while it is not in the process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag is set. data in s1dat remains stable as long as si is set. data in s1dat is always shifted from right to left: the first bit to be transmitted is the msb (bit 7), and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last data byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat. s1dat and the ack flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. the ack flag is controlled by the sio1 hardware and cannot be accessed by the cpu. serial data is shifted through the ack flag into s1dat on the rising edges of serial clock pulses on the scl line. when a byte has been shifted into s1dat, the serial data is available in s1dat, and the acknowledge bit is returned by the control logic during the ninth clock pulse. serial data is shifted out from s1dat via a buffer (bsd7) on the falling edges of clock pulses on the scl line. when the cpu writes to s1dat, bsd7 is loaded with the content of s1dat.7, which is the first bit to be transmitted to the sda line (see figure 36). after nine serial clock pulses, the eight bits in s1dat will have been transmitted to the sda line, and the acknowledge bit will be present in ack. note that the eight transmitted bits are shifted back into s1dat. table 53 address register s1dat (address dah) table 54 description of s1dat (dah) bits 76543210 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 bit symbol description 7 to 0 sd7 to sd0 eight bits to be transmitted or just received. a logic 1 in s1dat corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. serial data shifts through s1dat from right to left. figure 35 shows how data in s1dat is serially transferred to and from the sda line.
2000 jul 26 81 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.2.12 t he c ontrol r egister , s1con the cpu can read from and write to this 8-bit, directly addressable sfr. two bits are affected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c bus. the sto bit is also cleared when ens1 = 0. table 55 address register s1con (address d8h) table 56 description of s1con (d8h) bits 76543210 cr2 ens1 sta sto si aa cr1 cr0 bit symbol description 7 cr2 clock rate bit 2, see table 57. 6 ens1 enable serial i/o . ens1 = 0: i 2 c i/o disabled and reset. ens1 = 1: serial i/o enabled. 5sta start ag. when this bit is set in slave mode, the hardware checks the i 2 c-bus and generates a start condition if the bus is free or after the bus becomes free. if the device operates in master mode it will generate a repeated start condition. 4sto stop ?g . if this bit is set in a master mode a stop condition is generated. a stop condition detected on the i 2 c-bus clears this bit. this bit may also be set in slave mode in order to recover from an error condition. in this case no stop condition is generated to the i 2 c-bus, but the hardware releases the sda and scl lines and switches to the not selected receiver mode. the stop ?g is cleared by the hardware. 3si serial interrupt ?g. this ?g is set and an interrupt request is generated, after any of the following events occur: ? a start condition is generated in master mode. ? the own slave address has been received during aa = 1. ? the general call address has been received while s1adr.0 and aa = 1. ? a data byte has been received or transmitted in master mode (even if arbitration is lost). ? a data byte has been received or transmitted as selected slave. ? a stop or start condition is received as selected slave receiver or transmitter. while the si ?g is set, scl remains low and the serial transfer is suspended. si must be reset by software. 2aa assert acknowledge ag. when this bit is set, an acknowledge is returned after any one of the following conditions: ? own slave address is received. ? general call address is received (s1adr.0 = 1). ? a data byte is received, while the device is programmed to be a master receiver. ? a data byte is received. while the device is a selected slave receiver. when the bit is reset, no acknowledge is returned. consequently, no interrupt is requested when the own address or general call address is received. 1 cr1 clock rate bits 1 and 0; see table 57. 0 cr0
2000 jul 26 82 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.2.12.1 ens1, the sio1 enable bit ens1 = ?? when ens1 is ?? the sda and scl input signals are ignored, sio1 is in the not addressed slave state, and the sto bit in s1con is forced to 0. no other bits are affected. ens1 = ?? when ens1 is 1, i 2 c is enabled. note, that p1.6 and p1.7 have to set to open drain by writing the port mode registers p1m1.x and p1m2.x bits 6 and 7 with a 1 (see section 6.2 ?in description?. ens1 should not be used to temporarily release sio1 from the i 2 c bus since, when ens1 is reset, the i 2 c bus status is lost. the aa flag should be used instead (see description of the aa flag in the following text). in the following text, it is assumed that ens1 = 1. 15.2.12.2 sta, the start ?g sta = ?? when the sta bit is set to enter a master mode, the sio1 hardware checks the status of the i 2 c bus and generates a start condition if the bus is free. if the bus is not free, then sio1 waits for a stop condition (which will free the bus) and generates a start condition after a delay of a half clock period of the internal serial clock generator. if sta is set while sio1 is already in a master mode and one or more bytes are transmitted or received, sio1 transmits a repeated start condition. sta may be set at any time. sta may also be set when sio1 is an addressed slave. sta = ?? when the sta bit is reset, no start condition or repeated start condition will be generated. 15.2.12.3 sto, the stop flag sto = ?? when the sto bit is set while sio1 is in a master mode, a stop condition is transmitted to the i 2 c bus. when the stop condition is detected on the bus, the sio1 hardware clears the sto flag. in a slave mode, the sto flag may be set to recover from an error condition. in this case, no stop condition is transmitted to the i 2 c bus. however, the sio1 hardware behaves as if a stop condition has been received and switches to the defined not addressed slave receiver mode. the sto flag is automatically cleared by hardware. if the sta and sto bits are both set, the a stop condition is transmitted to the i 2 c bus if sio1 is in a master mode (in a slave mode, sio1 generates an internal stop condition which is not transmitted). sio1 then transmits a start condition. sto = ?? when the sto bit is reset, no stop condition will be generated.
2000 jul 26 83 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.35 serial input/output configuration. handbook, full pagewidth mhi036 ack bsd7 8 s1dat shift pulses sda scl internal bus fig.36 shift-in and shift-out timing. handbook, full pagewidth mhi037 d7 sda scl shift ack & s1dat shift bsd7 loaded by the cpu d6 d5 d4 d3 d2 d1 d0 a (2) (2) (2) (2) (2) (2) (2) (2) ack a (2) (1) (2) (2) (2) (2) (2) (2) (2) s1dat (1) d6 d7 d0 (3) d1 d2 d3 d4 d5 bsd7 shift out shift in (1) valid data in s1dat. (2) shifting data in s1dat and ack. (3) high level on sda.
2000 jul 26 84 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.2.12.4 si, the serial interrupt flag si = ?? when the si flag is set, then, if the ea and es1 (interrupt enable register) bits are also set, a serial interrupt is requested. si is set by hardware when one of 25 of the 26 possible sio1 states is entered. the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. a high level on the scl line is unaffected by the serial interrupt flag. si must be reset by software. si = 0: when the si flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the scl line. 15.2.12.5 aa, the assert acknowledge ?g aa = ?? if the aa flag is set, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: ? the ?wn slave address?has been received ? the general call address has been received while the general call bit (gc) in s1adr is set ? a data byte has been received while sio1 is in the master receiver mode ? a data byte has been received while sio1 is in the addressed slave receiver mode aa = ?? if the aa flag is reset, a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on scl when: ? a data has been received while sio1 is in the master receiver mode ? a data byte has been received while sio1 is in the addressed slave receiver mode when sio1 is in the addressed slave transmitter mode, state c8h will be entered after the last serial is transmitted (see figure 40). when si is cleared, sio1 leaves state c8h, enters the not addressed slave receiver mode, and the sda line remains at a high level. in state c8h, the aa flag can be set again for future address recognition. when sio1 is in the not addressed slave mode, its own slave address and the general call address are ignored. consequently, no acknowledge is returned, and a serial interrupt is not requested. thus, sio1 can be temporarily released from the i 2 c bus while the bus status is monitored. while sio1 is released from the bus, start and stop conditions are detected, and serial data is shifted in. address recognition can be resumed at any time by setting the aa flag. if the aa flag is set when the parts own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. 15.2.12.6 cr0, cr1, and cr2, the clock rate bits these three bits determine the serial clock frequency when sio1 is in a master mode. the various serial rates are shown in table 57. a 12.5 khz bit rate may be used by devices that interface to the i 2 c bus via standard i/o port lines which are software driven and slow. 100khz is usually the maximum bit rate and can be derived from a 16 mhz, 12 mhz, or a 6 mhz oscillator. a variable bit rate (0.5 khz to 62.5 khz) may also be used if timer 1 is not required for any other purpose while sio1 is in a master mode. the frequencies shown in table 57 are unimportant when sio1 is in a slave mode. in the slave modes, sio1 will automatically synchronize with any clock frequency up to 100 khz.
2000 jul 26 85 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.2.13 t he s tatus r egister , s1sta s1sta is an 8-bit read-only special function register. the three least significant bits are always zero. the five most significant bits contain the status code. there are 26 possible status codes. when s1sta contains f8h, no relevant state information is available and no serial interrupt is requested. all other s1sta values correspond to defined sio1 states. when each of these states is entered, a serial interrupt is requested (si = ??. a valid status code is present in s1sta one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. table 57 serial clock rate note 1. these frequencies exceed the upper limit of 100 khz of the standard i 2 c-bus specification. cr2 cr1 cr0 bit frequency (khz) at f clk f clk divided by 6 mhz 8 mhz 12 mhz 0 0 0 47 62.5 94 128 0 0 1 54 71 107 (1) 112 0 1 0 63 83.3 125 (1) 96 0 1 1 75 100 150 (1) 80 1 0 0 12.5 17 25 480 1 0 1 100 133 (1) 200 (1) 60 1 1 0 200 267 (1) 400 (1) 30 111 0.49 > 62.5 0 < 254 0.65 < 55.6 0 < 253 0.98 < 50.0 0 < 251 48 x (256 (reload value timer 1)) reload value timer 1 in mode 2. 15.2.14 m ore i nformation on sio1 o perating m odes the four operating modes are: ? master transmitter ? master receiver ? slave receiver ? slave transmitter data transfers in each mode of operation are shown in figures 37 to 40. these figures contain the following abbreviations: abbreviation explanation s start condition sla 7-bit slave address r read bit (high level at sda) w write bit (low level at sda) a acknowledge bit (low level at sda) a not acknowledge bit (high level at sda) data 8-bit data byte p stop condition in figures 37 to 40, circles are used to indicate when the serial interrupt flag is set. the numbers in the circles show the status code held in the s1sta register. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. when a serial interrupt routine is entered, the status code in s1sta is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in tables 61 to 65. 15.2.14.1 master transmitter mode: in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see figure 37). before the master transmitter mode can be entered, s1con must be initialized as in table 58. cr0, cr1, and cr2 define the serial bit rate. ens1 must be set to logic 1 to enable sio1. if the aa bit is reset, sio1 will not acknowledge its own slave address or the general call address in the event of another device becoming
2000 jul 26 86 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 master of the bus. in other words, if aa is reset, sio0 cannot enter a slave mode. sta, sto, and si must be reset. the master transmitter mode may now be entered by setting the sta bit using the setb instruction. the sio1 logic will now test the i 2 c bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag (si) is set, and the status code in the status register (s1sta) will be 08h. this status code must be used to vector to an interrupt service routine that loads s1dat with the slave address and the data direction bit (sla+w). the si bit in s1con must then be reset before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. there are 18h, 20h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 61. after a repeated start condition (state 10h). sio1 may switch to the master receiver mode by loading s1dat with sla+r). table 58 address register s1con (address d8h) 76543210 cr2 ens1 sta sto si aa cr1 cr0 bit rate 1 0 0 0 x bit rate 15.2.14.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 38). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load s1dat with the 7-bit slave address and the data direction bit (sla+r). the si bit in s1con must then be cleared before the serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. these are 40h, 48h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 62. ens1, cr1, and cr0 are not affected by the serial transfer and are not referred to in table 62. after a repeated start condition (state 10h), sio1 may switch to the master transmitter mode by loading s1dat with sla+w. 15.2.14.3 slave receiver mode: in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 39). to initiate the slave receiver mode, s1adr and s1con must be loaded as in table 59. the upper 7 bits are the address to which sio1 will respond when addressed by a master. if the lsb (gc) is set, sio1 will respond to the general call address (00h); otherwise it ignores the general call address. cr0, cr1, and cr2 do not affect sio1 in the slave mode. ens1 must be set to logic 1 to enable sio1. the aa bit must be set to enable sio1 to acknowledge its own slave address or the general call address. sta, sto, and si must be reset. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be ? (w) for sio1 to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag (i) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 63. the slave receiver mode may also be entered if arbitration is lost while sio1 is in the master mode (see status 68h and 78h). if the aa bit is reset during a transfer, sio1 will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus.
2000 jul 26 87 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 59 address register s1adr (dbh) (address 00h) table 60 address register s1con (d8h) (address 00h) 76543210 xxxxxxxgc own slave address 76543210 cr2 ens1 sta sto si aa cr1 cr0 x10001xx fig.37 format and states in the master transmitter mode. handbook, full pagewidth mhi038 n this number (contained in s1sta) corresponds to a defined state of the i 2 c-bus a any number of data bytes and their associated acknowledge bits from slave to master from master to slave successful transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave sla s p wa mt 18h p a 20h other mst continues 38h 08h sla s w r 10h to mst/rec mode entry = mr data data a 28h other mst continues 38h aora aora a other mst continues to corresponding states in slave mode 68h 78h 80h p a 30h (see table 61)
2000 jul 26 88 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.38 format and states in the master receiver mode. handbook, full pagewidth mhi039 n this number (contained in s1sta) corresponds to a defined state of the i 2 c-bus a any number of data bytes and their associated acknowledge bits from slave to master from master to slave successful reception from a slave transmitter next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or acknowledge bit arbitration lost and addressed as slave sla s p ra mr 40h p a 48h a other mst continues 38h a 50h 08h sla s r w 10h to mst/trx mode entry = mt data data a 58h data aora other mst continues 38h a other mst continues to corresponding states in slave mode 68h 78h 80h ( see table 62)
2000 jul 26 89 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.39 format and states in the slave receiver mode. handbook, full pagewidth mhi040 n this number (contained in s1sta) corresponds to a defined state of the i 2 c-bus a any number of data bytes and their associated acknowledge bits from slave to master from master to slave reception of the own slave address and one or more data bytes all are acknowledged last data byte received is not acknowledged arbitration lost as mst and addressed as slave reception of the general call address and one or more data bytes last data byte is not acknowledged arbitration lost as mst and addressed as slave by general call sla s wa 60h a 68h data data a 80h a p or s data a 80h a0h p or s 88h general call a 70h a 78h data a 90h a p or s data 90h a0h p or s 98h a (see table 63)
2000 jul 26 90 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.40 format and states of the slave transmitter mode. handbook, full pagewidth reception of the own slave address and transmission of one or more data bytes arbitration lost as mst and addressed as slave last data byte transmitted. switched to not addressed slave (aa bit in s1con = "0") p or s a b0h a all "1"s c8h mhi041 n this number (contained in s1sta) corresponds to a defined state of the i 2 c-bus. see table 9. a any number of data bytes and their associated acknowledge bits from slave to master from master to slave data sla s p or s ra a8h a b8h data a c0h data (see table 64)
2000 jul 26 91 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 61 master transmitter mode status code (s1sta) status of the i 2 c bus and sio1 hardware application software response next action taken by sio1 hardware to/from s1dat to s1con sta sto si aa 08h a start condition has been transmitted load sla+w x 0 0 x sla+w will be transmitted; ack bit will received 10h a repeated start condition has been transmitted load sla+w or x 0 0 x as above load sla+r x 0 0 x sla+w will be transmitted; sio1 will be switched to mst/rec mode 18h sla+w has been transmitted; ack has been received load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received been received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto ?g will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto ?g will be reset 20h sla+w has been transmitted; not ack has been received load data byte or 0 0 0 x data byte will be transmitted; ack will be received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto ?g will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto ?g will be reset 28h data byte in s1dat has been transmitted; ack has been received load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto ?g will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto ?g will be reset 30h data byte in s1dat has been transmitted; not ack has been received load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto ?g will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto ?g will be reset 38h arbitration lost in sla+r/ w or data bytes no s1dat action or 0 0 0 x i 2 c bus will be released; not addressed slave will be entered no s1dat action 1 0 0 x a start condition will be transmitted when the bus becomes free
2000 jul 26 92 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 62 master receiver mode status code (s1sta) status of the i 2 c bus and sio1 hardware application software response next action taken by sio1 hardware to/from s1dat to s1con sta sto si aa 08h a start condition has been transmitted load sla+wr x 0 0 x sla+r will be transmitted; ack bit will be received 10h a repeated start condition has been transmitted load sla+r or x 0 0 x as above load sla+w x 0 0 x sla+w will be transmitted; sio1 will be switched to mst/trx mode 38h arbitration lost in not ack bit no s1dat action or 0 0 0 x i 2 c bus will be released; sio1 will enter a slave mode no s1dat action 1 0 0 x a start condition will be transmitted when the bus becomes free 40h sla+r has been transmitted; ack has been received no s1dat action or 0 0 0 0 data byte will be received; not ack bit will be returned no s1dat action 0 0 0 1 data byte will be received; ack bit will be returned 48h sla+r has been transmitted; not ack has been received no s1dat action or 1 0 0 x repeated start condition will be transmitted no s1dat action or 0 1 0 x stop condition will be transmitted; sto ?g will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto ?g will be reset 50h data byte has been received; not ack has been returned read data byte or 0 0 0 0 data byte will be received; not ack bit will be returned read data byte 0 0 0 1 data byte will be received; ack bit will be returned 58h data byte has been received; ack has been returned read data byte or 1 0 0 x repeated start condition will be transmitted read data byte or 0 1 0 x stop condition will be transmitted; sto ?g will be reset read data byte 1 1 0 x stop condition followed by a start condition will be transmitted; sto ?g will be reset
2000 jul 26 93 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 63 slave receiver mode status code (s1sta) status of the i 2 c bus and sio1 hardware application software response next action taken by sio1 hardware to/from s1dat to s1con sta sto si aa 60h own sla+w has been received; ack has been returned no s1dat action or x 0 0 0 data byte will be received and not ack will be returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 68h arbitration lost in sla+r/w as master; own sla+w has been received, ack returned no s1dat action or x 0 0 0 data byte will be received and not ack will be returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 70h general call address (00h) has been received; ack has been returned no s1dat action or x 0 0 0 data byte will be received and not ack will be returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 78h arbitration lost in sla+r/ w as master; general call address has been received, ack has been returned no s1dat action or x 0 0 0 data byte will be received and not ack will be returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 80h previously addressed with own slv address; data has been received; ack has been returned read data byte or x 0 0 0 data byte will be received and not ack will be returned read data byte x 0 0 1 data byte will be received and ack will be returned 88h previously addressed with own sla; data byte has been received; not ack has been returned read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. 90h previously addressed with general call; data byte has been received; ack has been returned read data byte or x 0 0 0 data byte will be received and not ack will be returned read data byte x 0 0 1 data byte will be received and ack will be returned
2000 jul 26 94 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 98h previously addressed with general call; data byte has been received; not ack has been returned read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx no stdat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address no stdat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 no stdat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free no stdat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. status code (s1sta) status of the i 2 c bus and sio1 hardware application software response next action taken by sio1 hardware to/from s1dat to s1con sta sto si aa
2000 jul 26 95 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 64 slave transmitter mode status code (s1sta) status of the i 2 c bus and sio1 hardware application software response next action taken by sio1 hardware to/from s1dat to s1con sta sto si aa a8h own sla+r has been received; ack has been returned load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received load data byte x 0 0 1 data byte will be transmitted; ack will be received b0h arbitration lost in sla+r/w as master; own sla+r has been received, ack has been returned load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received load data byte x 0 0 1 data byte will be transmitted; ack bit will be received b8h data byte in s1dat has been transmitted; ack has been received load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received load data byte x 0 0 1 data byte will be transmitted; ack bit will be received c0h data byte in s1dat has been transmitted; not ack has been received no s1dat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address no s1dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 no s1dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free no s1dat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. c8h last data byte in s1dat has been transmitted (aa = 0); ack has been received no s1dat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address no s1dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 no s1dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free no s1dat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
2000 jul 26 96 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 65 miscellaneous states status code (s1sta) status of the i 2 c bus and sio1 hardware application software response next action taken by sio1 hardware to/from s1dat to s1con sta sto si aa f8h no relevant state information available; si = 0 no s1dat action no s1con action wait or proceed current transfer 00h bus error during mst or selected slave modes, due to an illegal start or stop condition. state 00h can also occur when interference causes sio1 to enter an unde?ed state. no s1dat action 0 1 0 x only the internal hardware is affected in the mst or addressed slv modes. in all cases, the bus is released and sio1 is switched to the not addressed slv mode. sto is reset.
2000 jul 26 97 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.2.14.4 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 40). data transfer is initialized as in the slave receiver mode. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be ? (r) for sio1 to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 64. the slave transmitter mode may also be entered if arbitration is lost while sio1 is in the master mode (see state b0h). if the aa bit is reset during a transfer, sio1 will transmit the last byte of the transfer and enter state c0h or c8h. sio1 is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the master receiver receives all 1s as serial data. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored, and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus. 15.2.14.5 miscellaneous states there are two s1sta codes that do not correspond to a defined sio1 hardware state (see table 65). these are discussed below. s1sta = f8h: this status code indicates that no relevant information is available because the serial interrupt flag, si, is not yet set. this occurs between other states and when sio1 is not involved in a serial transfer. s1sta = 00h: this status code indicates that a bus error has occurred during an sio1 serial transfer. a bus error is caused when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interference disturbs the internal sio1 signals. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this causes sio1 to enter the not addressed slave mode (a defined state) and to clear the sto flag (no other bits in s1con are affected). the sda and scl lines are released (a stop condition is not transmitted). 15.2.15 s ome s pecial c ases the sio1 hardware has facilities to handle the following special cases that may occur during a serial transfer: simultaneous repeated start conditions from two masters. a repeated start condition may be generated in the master transmitter or master receiver modes. a special case occurs if another master simultaneously generates a repeated start condition (see figure 41). until this occurs, arbitration is not lost by either master since they were both transmitting the same data. if the sio1 hardware detects a repeated start condition on the i 2 c bus before generating a repeated start condition itself, it will release the bus, and no interrupt request is generated. if another master frees the bus by generating a stop condition, sio1 will transmit a normal start condition (state 08h), and a retry of the total serial data transfer can commence. 15.2.15.1 data transfer after loss of arbitration arbitration may be lost in the master transmitter and master receiver modes (see figure 33). loss of arbitration is indicated by the following states in s1sta; 38h, 68h, 78h, and b0h (see figures 37 and 38). if the sta flag in s1con is set by the routines which service these states, then, if the bus is free again, a start condition (state 08h) is transmitted without intervention by the cpu, and a retry of the total serial transfer can commence. 15.2.15.2 forced access to the i 2 c bus in some applications, it may be possible for an uncontrolled source to cause a bus hang-up. in such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between sda and scl. if an uncontrolled source generates a superfluous start or masks a stop condition, then the i 2 c bus stays busy indefinitely. if the sta flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the i 2 c bus is possible. this is achieved by setting the sto flag while the sta flag is still set. no stop condition is transmitted. the sio1 hardware behaves as if a stop condition was received and is able to transmit a start condition. the sto flag is cleared by hardware (see figure 42).
2000 jul 26 98 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.41 simultaneous repeated start conditions from 2 masters. handbook, full pagewidth mhi042 swa s as p data sla other mst continues other master sends repeated start condition earlier retry sla 08h 18h 28h 08h fig.42 forces access to a busy i 2 c bus. handbook, full pagewidth mhi043 sta flag sto flag sda line scl line time limit start condition
2000 jul 26 99 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.2.15.3 i 2 c bus obstructed by a low level on scl and sda an i 2 c bus hang-up occurs if sda or scl is pulled low by an uncontrolled source. if the scl line is obstructed (pulled low) by a device on the bus, no further serial transfer is possible, and the sio1 hardware cannot resolve this type of problem. when this occurs, the problem must be resolved by the device that is pulling the scl bus line low. if the sda line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the scl line (see figure 43). the sio1 hardware transmits additional clock pulses when the sta flag is set, but no start condition can be generated because the sda line is pulled low while the i 2 c bus is considered free. the sio1 hardware attempts to generate a start condition after every two additional clock pulses on the scl line. when the sda line is eventually released, a normal start condition is transmitted, state 08h is entered, and the serial transfer continues. if a forced bus access occurs or a repeated start condition is transmitted while sda is obstructed (pulled low), the sio1 hardware performs the same action as described above. in each case, state 08h is entered after a successful start condition is transmitted and normal serial transfer continues. note that the cpu is not involved in solving these bus hang-up problems. 15.2.15.4 bus error a bus error occurs when a start or stop condition is present at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. the sio1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. when a bus error is detected, sio1 immediately switches to the not addressed slave mode, releases the sda and scl lines, sets the interrupt flag, and loads the status register with 00h. this status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in table 65. fig.43 recovering from a bus obstruction caused by a low level on sda. handbook, full pagewidth mhi044 sta flag sda line scl line (1) (1) (2) (3) start condition (1) unsuccessful attempt to send a start condition. (2) sda line released. (3) successful attempt to send a start condition; state d8h is centered.
2000 jul 26 100 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.3 software examples of sio1 service routines this section consists of a software example for: ? initialization of sio1 after a reset ? entering the sio1 interrupt routine ? the 26 state service routines for the master transmitter mode master receiver mode slave receiver mode slave transmitter mode 15.3.1 i nitialization in the initialization routine, sio1 is enabled for both master and slave modes. for each mode, a number of bytes of internal data ram are allocated to the sio to act as either a transmission or reception buffer. in this example, 8 bytes of internal data ram are reserved for different purposes. the data memory map is shown in figure 44. the initialization routine performs the following functions: ? s1adr is loaded with the parts own slave address and the general call bit (gc) ? p1.6 and p1.7 bit latches are loaded with logic 1s ? ram location hadd is loaded with the high-order address byte of the service routines ? the sio1 interrupt enable and interrupt priority bits are set ? the slave mode is enabled by simultaneously setting the ens1 and aa bits in s1con and the serial clock frequency (for master modes) is defined by loading cr0 and cr1 in s1con. the master routines must be started in the main program. the sio1 hardware now begins checking the i 2 c bus for its own slave address and general call. if the general call or the own slave address is detected, an interrupt is requested and s1sta is loaded with the appropriate state information. the following text describes a fast method of branching to the appropriate service routine. 15.3.2 sio1 i nterrupt r outine when the sio1 interrupt is entered, the psw is first pushed on the stack. then s1sta and hadd (loaded with the high-order address byte of the 26 service routines by the initialization routine) are pushed on to the stack. s1sta contains a status code which is the lower byte of one of the 26 service routines. the next instruction is ret, which is the return from subroutine instruction. when this instruction is executed, the high and low order address bytes are popped from stack and loaded into the program counter. the next instruction to be executed is the first instruction of the state service routine. seven bytes of program code (which execute in eight machine cycles) are required to branch to one of the 26 state service routines. si push psw save psw push s1sta push status code (low order address byte) push hadd push high order address byte ret jump to state service routine the state service routines are located in a 256-byte page of program memory. the location of this page is defined in the initialization routine. the page can be located anywhere in program memory by loading data ram register hadd with the page number. page 01 is chosen in this example, and the service routines are located between addresses 0100h and 01ffh. 15.3.3 t he s tat e s ervice r outine the state service routines are located 8 bytes from each other. eight bytes of code are sufficient for most of the service routines. a few of the routines require more than 8 bytes and have to jump to other locations to obtain more bytes of code. each state routine is part of the sio1 interrupt routine and handles one of the 26 states. it ends with a reti instruction which causes a return to the main program.
2000 jul 26 101 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.44 sio1 data memory map. handbook, full pagewidth mhi045 cr0 cr1 aa si st0 special function registers sta ens1 cr2 s1con psw ipo ien0 p1 s1sta s1dat s1adr d8 d0 b8 ab 90 80 7f d9 da db 0 0 0 gc ps1 es1 ea p1.6 p1.7 internal data ram higher address byte interrupt routine slave transmitter data ram sla + r/w to be transmitted to sla number of bytes as master hadd std sla numbytmst backup original value of numbytmst r0 r1 slave receiver data ram srd master receiver data ram mrd master transmitter data ram mtd 50 4f 48 51 52 53 40 38 30 19 18 00
2000 jul 26 102 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 15.3.4 m aster t ransmitter and m aster r eceiver m odes the master mode is entered in the main program. to enter the master transmitter mode, the main program must first load the internal data ram with the slave address, data bytes, and the number of data bytes to be transmitted. to enter the master receiver mode, the main program must first load the internal data ram with the slave address and the number of data bytes to be received. the r/w bit determines whether sio1 operates in the master transmitter or master receiver mode. master mode operation commences when the sta bit in s1cion is set by the setb instruction and data transfer is controlled by the master state service routines in accordance with table 61, table 62, figure 37 and figure 38. in the example below, 4 bytes are transferred. there is no repeated start condition. in the event of lost arbitration, the transfer is restarted when the bus becomes free. if a bus error occurs, the i 2 c bus is released and sio1 enters the not selected slave receiver mode. if a slave device returns a not acknowledge, a stop condition is generated. a repeated start condition can be included in the serial transfer if the sta flag is set instead of the sto flag in the state service routines vectored to by status codes 28h and 58h. additional software must be written to determine which data is transferred after a repeated start condition. 15.3.5 s lave t ransmitter and s lave r eceiver m odes after initialization, sio1 continually tests the i 2 c bus and branches to one of the slave state service routines if it detects its own slave address or the general call address (see table 63, table 64, figure 39, and figure 40). if arbitration was lost while in the master mode, the master mode is restarted after the current transfer. if a bus error occurs, the i 2 c bus is released and sio1 enters the not selected slave receiver mode. in the slave receiver mode, a maximum of 8 received data bytes can be stored in the internal data ram. a maximum of 8 bytes ensures that other ram locations are not overwritten if a master sends more bytes. if more than 8 bytes are transmitted, a not acknowledge is returned, and sio1 enters the not addressed slave receiver mode. a maximum of one received data byte can be stored in the internal data ram after a general call address is detected. if more than one byte is transmitted, a not acknowledge is returned and sio1 enters the not addressed slave receiver mode. in the slave transmitter mode, data to be transmitted is obtained from the same locations in the internal data ram that were previously loaded by the main program. after a not acknowledge has been returned by a master receiver device, sio1 enters the not addressed slave mode. 15.3.6 a dapting t he s oftware f or d ifferent a pplications the following software example shows the typical structure of the interrupt routine including the 26 state service routines and may be used as a base for user applications. if one or more of the four modes are not used, the associated state service routines may be removed but, care should be taken that a deleted routine can never be invoked. this example does not include any time-out routines. in the slave modes, time-out routines are not very useful since, in these modes, sio1 behaves essentially as a passive device. in the master modes, an internal timer may be used to cause a time-out if a serial transfer is not complete after a defined period of time. this time period is defined by the system connected to the i 2 c bus.
2000 jul 26 103 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 si01 equate list loc obj source !***************************************************************************************************************************** ! locations of the si01 special function registers! !***************************************************************************************************************************** 00d8 s1con -0xd8 00d9 s1sta -0xd9 00da s1dat -0xda 00db s1adr -0xdb 00a8 ien0 -0xa8 00b8 ip0 02b8 !***************************************************************************************************************************** ! bit locations !***************************************************************************************************************************** 00dd sta -0xdd ! sta bit in s1con 00bd si01hp -0xbd ! ip0, si01 priority bit !***************************************************************************************************************************** ! immediate data to write into register s1con !***************************************************************************************************************************** 00d5 ens1_notsta_sto_notsi_aa_cr0 -0xd5 ! generates stop ! (cr0 = 100khz @ f osc = !6 mhz) 00c5 ens1_notsta_notsto_notsi_aa_cr0 -0xc5 ! releases bus and ack ! 00c1 ens1_notsta_notsto_notsi_notaa_cr0 -0xc1 ! releases bus and ! not ack 00e5 ens1_sta_notsto_notsi_aa_cr0 -0xe5 ! releases bus and set ! sta !***************************************************************************************************************************** ! general immediate data !***************************************************************************************************************************** 0031 ownsla -0x31 ! own sla+general call ! must be written into s1adr 00a0 ensi01 -0xa0 ! ea+es1, enable sio1 interrupt ! must be written into ien0 0001 pag1 -0x01 ! select pag1 as hadd 00c0 slaw -0xc0 ! sla+w to be transmitted 00c1 slar -0xc1 ! sla+r to be transmitted 0018 selrb3 -0x18 ! select register bank 3
2000 jul 26 104 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 !***************************************************************************************************************************** ! locations in data ram !***************************************************************************************************************************** 0030 mtd -0x30 ! mst/trx/data base address 0038 mrd -0x38 ! mst/rec/data base address 0040 srd -0x40 ! slv/rec/data base address 0048 std -0x48 ! slv/trx/data base address 0053 backup -0x53 ! backup from numbytmst ! to restore numbytmst in case ! of an arbitration loss. 0052 numbytmst -0x52 ! number of bytes to transmit ! or receive as mst. 0051 sla -0x51 ! contains sla+r/w to be ! transmitted. 0050 hadd -0x50 ! high address byte for state 0f ! till state 25. !***************************************************************************************************************************** ! initialization routine ! example to initialize iic interface as slave receiver or slave transmitter and start a master transmit ! or a master receive function. 4 bytes will be transmitted or received. !***************************************************************************************************************************** .sect strt .base 0x00 0000 4100 ajmp init ! reset .sect initial .base 0x200 0200 75db31 init: mov s1adr,#ownsla ! load own sla + enable ! general call recognition 0203 d296 setb p1(6) ! p1.6 high level. 0205 d297 setb p1(7) ! p1.7 high level. 0207 755001 mov hadd,#pag1 020a 43a8a0 orl ien0,#ensi01 ! enable si01 interrupt 020d c2bd clr si01hp ! si01 interrupt low priority 020f 75d8c5 mov s1con, #ens1_notsta_notsto_notsi_aa_cr0 ! initialize slv funct. !***************************************************************************************************************************** ! start master transmit function !***************************************************************************************************************************** 0212 755204 mov numbytmst,#0x4 ! transmit 4 bytes. 0215 7551c0 mov sla,#slaw ! sla+w, transmit funct. 0218 d2dd setb sta ! set sta in s1con! !***************************************************************************************************************************** ! start master receive function !***************************************************************************************************************************** 021a 755204 mov numbytmst,#0x4 ! receive 4 bytes. 021d 7551c1 mov sla,#slar ! sla+r, receive funct. 0220 d2dd setb sta ! set sta in s1con loc obj source
2000 jul 26 105 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 !***************************************************************************************************************************** ! si01 interrupt routine !***************************************************************************************************************************** .sect intvec ! si01 interrupt vector .base 0x00 ! s1sta and hadd are pushed onto the stack. ! they serve as return address for the ret instruction. ! the ret instruction sets the program counter to address hadd, ! s1sta and jumps to the right subroutine. 002b c0d0 push psw ! save psw 002d c0d9 push s1sta 002f c050 push hadd 0031 22 ret ! jmp to address hadd,s1sta. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 00, bus error. ! action : enter not addressed slv mode and release bus. sto reset. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect st0 .base 0x100 0100 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! clr si ! set sto,aa 0103 d0d0 pop psw 0105 32 reti !***************************************************************************************************************************** ! master state service routines !***************************************************************************************************************************** !***************************************************************************************************************************** ! state 08 and state 10 are both for mst/trx and mst/rec. ! the r/w bit decides whether the next state is within ! mst/trx mode or within mst/rec mode. !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 08, a, start condition has been transmitted. ! action : sla+r/w are transmitted, ack bit is received.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts8 .base 0x108 0108 8551da mov s1dat,sla ! load sla+r/w 010b 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si 010e 01a0 ajmp initbase1 loc obj source
2000 jul 26 106 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : state : 10, a repeated start condition has been transmitted. ! action : sla+r/w are transmitted, ack bit is received.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts10 .base 0x110 0110 8551da mov s1dat,sla ! load sla+r/w 0113 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si 010e 01a0 ajmp initbase1 .sect ibase1 .base 0xa0 00a0 75d018 initbase1: mov psw,#selrb3 00a3 7930 mov r1,#mtd 00a5 7838 mov r0,#mrd 00a7 855253 mov backup,numbytmst ! save initial value 00aa d0d0 pop psw 00ac 32 reti !***************************************************************************************************************************** ! master transmitter state service routines !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 18, previous state was state 8 or state 10, sla+w have been transmitted, ack been received. ! action : first data is transmitted, ack bit is received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -dc .sect mts18 .base 0x118 0118 75d018 mov psw,#selrb3 011b 87da mov s1dat,@r1 011d 01b5 ajmp con !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 20, sla+w have been transmitted, not ack has been received ! action : transmit stop condition.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts20 .base 0x120 0120 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! set sto, clr si 0123 d0d0 pop psw 0125 32 reti loc obj source
2000 jul 26 107 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 28, data of s1dat have been transmitted, ack received. ! action : if transmitted data is last data then transmit a stop condition, else transmit next data. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts28 .base 0x128 0128 d55285 djnz numbytmst,notldat1 ! jmp if not last data 012b 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! clr si, set aa 012e 01b9 ajmp retmt .sect mts28sb .base 0x0b0 00b0 75d018 notldat1: mov psw,#selrb3 00b3 87da mov s1dat,@r1 00b5 75d8c5 con: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00b8 09 inc r1 00b9 d0d0 retmt : pop psw 00bb 32 reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 30, data of s1dat have been transmitted, not ack received. ! action : transmit a stop condition. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts30 .base 0x130 0130 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! set sto, clr si 0133 d0d0 pop psw 0135 32 reti! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 38, arbitration lost in sla+w or data. ! action : bus is released, not addressed slv mode is entered. a new start condition is ! transmitted when the iic bus is free again.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts38 .base 0x138 0138 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 013b 855352 mov numbytmst,backup 013e 01b9 ajmp retmt !***************************************************************************************************************************** ! master receiver state service routines !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 40, previous state was state 08 or state 10, sla+r have been transmitted, ack received. ! action : data will be received, ack returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts40 .base 0x140 0140 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr sta, sto, si set aa 0143 d0d0 pop psw 32 reti loc obj source
2000 jul 26 108 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 48, sla+r have been transmitted, not ack received. ! action : stop condition will be generated. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts48 .base 0x148 0148 75d8d5 stop: mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! set sto, clr si 014b d0d0 pop psw 014d 32 reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 50, data have been received, ack returned. ! action : read data of s1dat. data will be received, if it is last data then not ack will be returned ! else ack will be returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mrs50 .base 0x150 0150 75d018 mov psw,#selrb3 0153 a6da mov @r0,s1dat ! read received data 0155 01c0 ajmp rec1 .sect mrs50s .base 0xc0 00c0 d55205 rec1: djnz numbytmst,notldat2 00c3 75d8c1 mov s1con,#ens1_notsta_notsto_notsi_notaa_cr0 ! clr si,aa 00c6 8003 sjmp retmr 00c8 75d8c5 notldat2: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00cb 08 retmr: inc r0 00cc d0d0 pop psw 00ce 32 reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 58, data have been received, not ack returned. ! action : read data of master state service routiness1dat and generate a stop condition. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mrs58 .base 0x158 0158 75d018 mov psw,#selrb3 015b a6da mov @r0,s1dat 015d 80e9 sjmp stop loc obj source
2000 jul 26 109 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 !***************************************************************************************************************************** ! slave receiver state service routines !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 60, own sla+w have been received, ack returned. ! action : data will be recmaster state service routineseived and ack returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs60 .base 0x160 0160 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 0163 75d018 mov psw,#selrb3 0166 01d0 ajmp initsrd .sect insrd .base 0xd0 00d0 7840 initsrd: mov r0,#srd 00d2 7908 mov r1,#8 00d4 d0d0 pop psw 00d6 32 reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 68, arbitration lost in sla and r/w as mst own sla+w have been received, ack returned ! action : data will be received and ack returned. sta is set to restart mst mode after the bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs68 .base 0x168 0168 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 016b 75d018 mov psw,#selrb3 016e 01d0 ajmp initsrd !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 70, general call has been received, ack returned. ! action : data will be received and ack returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs70 .base 0x170 0170 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 0173 75d018 mov psw,#selrb3 ! initialize srd counter 0176 01d0 ajmp initsrd !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 78, arbitration lost in sla+r/w as mst. general call has been received, ack returned. ! action : data will be received and ack returned. sta is set to restart mst mode after the bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs78 .base 0x178 0178 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 017b 75d018 mov psw,#selrb3 ! initialize srd counter 017e 01d0 ajmp initsrd loc obj source
2000 jul 26 110 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 80, previously addressed with own sla. data received, ack returned. ! action : read data. ! if received data was the last ! then super?ous data will be received and not ack returned ! else next data will be received and ack returned.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs80 .base 0x180 0180 75d018 mov psw,#selrb3 0183 a6da mov @r0,s1dat ! read received data 0185 01d8 ajmp rec2 .sect srs80s .base 0xd8 00d8 d906 rec2: djnz r1,notldat3 00da 75d8c1 ldat: mov s1con,#ens1_notsta_notsto_notsi_notaa_cr0 ! clr si,aa 00dd d0d0 pop psw 00df 32 reti 00e0 75d8c5 notldat3: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00e3 08 inc r0 00e4 d0d0 retsr: pop psw 00e6 32 reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 88, previously addressed with own sla. data received not ack returned. ! action : no save of data, enter not addressed slv mode. ! recognition of own sla. general call recognized, if s1adr. 01.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs88 .base 0x188 0188 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 018b 01e4 ajmp retsr !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 90, previously addressed with general call. data has been received, ack has been returned. ! action : read data. ! after general call only one byte will be received with ack the second data ! will be received with not ack. ! data will be received and not ack returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs90 .base 0x190 0190 76d018 mov psw,#selrb3 0193 a6da mov @r0,s1dat ! read received data 0195 01da ajmp ldat loc obj source
2000 jul 26 111 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : 98, previously addressed with general call. ! data has been received, not ack has been returned. ! action : no save of data, enter not addressed slv mode. ! recognition of own sla. general call recognized, if s1adr. 01.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs98 .base 0x198 0198 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 019b d0d0 pop psw 019d 32 reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : a0, a stop condition or repeated start has been received, while still addressed as ! slv/rec or slv/trx. ! action : no save of data, enter not addressed slv mode. ! recognition of own sla. general call recognized, if s1adr. 01. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srsa0 .base 0x1a0 01a0 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01a3 d0d0 pop psw 01a5 32 reti !***************************************************************************************************************************** ! slave transmitter state service routines !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : a8, own sla+r received, ack returned. ! action : data will be transmitted, a bit received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect stsa8 .base 0x1a8 01a8 8548da mov s1dat,std ! load data in s1dat 01ab 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01ae 01e8 ajmp initbase2 .sect ibase2 .base 0xe8 00e8 75d018 initbase2: mov psw,#selrb3 00eb 7948 mov r1, #std 00ed 09 inc r1 00ee d0d0 pop psw 00f0 32 reti loc obj source
2000 jul 26 112 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : b0, arbitration lost in sla and r/w as mst. own sla+r received, ack returned. ! action : data will be transmitted, a bit received. ! sta is set to restart mst mode after the bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect sstsb0 .base 0x1b0 01b0 8548da mov s1dat,std ! load data in s1dat 01b3 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 01b6 01e8 ajmp initbase2 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : b8, data has been transmitted, ack received. ! action : data will be transmitted, ack bit is received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect stsb8 .base 0x1b8 01b8 75d018 mov psw,#selrb3 01bb 87da mov s1dat,@r1 01bd 01f8 ajmp scon .sect scn .base 0xf8 00f8 75d8c5 scon: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00fb 09 inc r1 00fc d0d0 pop psw 00fe 32 reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : c0, data has been transmitted, not ack received. ! action : enter not addressed slv mode. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect stsc0 .base 0x1c0 01c0 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01c3 d0d0 pop psw 01c5 32 reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! state : c8, last data has been transmitted (aa=0), ack received. ! action : enter not addressed slv mode !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect stsc8 .base 0x1c8 01c8 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01cb d0d0 pop psw 01cd 32 reti !***************************************************************************************************************************** ! end of si01 interrupt routine !***************************************************************************************************************************** loc obj source
2000 jul 26 113 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 16 timer 2 16.1 features of timer 2 timer t2 is a 16-bit timer consisting of two registers tmh2 (high byte) and tml2 (low byte). the 16-bit timer/counter can be switched off or clocked via a prescaler from one of two sources: f clk /6 or an external signal. when timer t2 is configured as a counter, the prescaler is clocked by an external signal on t2 (p3.o). a rising edge on t2 increments the prescaler, and the maximum repetition rate is one count per machine cycle (1 mhz with a 6 mhz oscillator). the maximum repetition rate for timer t2 is twice the maximum repetition rate for timer 0 and timer 1. t2 (p3.0) is sampled at s2p1 and again at s5p1 (i.e., twice per machine cycle). a rising edge is detected when t2 is low during one sample and high during the next sample. to ensure that a rising edge is detected, the input signal must be low for at least 1 ? 2 cycle and then high for at least 1 ? 2 cycle. if a rising edge is detected before the end of s2p1, the timer will be incremented during the following cycle; otherwise it will be incremented one cycle later. the prescaler has a programmable division factor of 1, 2, 4, or 8 and is cleared if its division factor or input source is changed, or if the timer/counter is reset. timer t2 may be read ?n the fly but possesses no extra read latches, and software precautions may have to be taken to avoid misinterpretation in the event of an overflow from least to most significant byte while timer t2 is being read. timer t2 is not loadable and is reset by the rst signal or by a rising edge on the input signal rt2, if enabled. rt2 is enabled by setting bit t2er (tm2con.5). when the least significant byte of the timer overflows or when a 16-bit overflow occurs, an interrupt request may be generated. either or both of these overflows can be programmed to request an interrupt. in both cases, the interrupt vector will be the same. when the lower byte (tml2) overflows, flag t2b0 (tm2con) is set and flag t20v (tm2lr) is set when tmh2 overflows. these flags are set one cycle after an overflow occurs. note that when t20v is set, t2b0 will also be set. to enable the byte overflow interrupt, bits et2 (len1.7, enable overflow interrupt, see table 67) and t2ls0 (tm2con.6, byte overflow interrupt select) must be set. bit twbo (tm2con.4) is the timer t2 byte overflow flag. to enable the 16-bit overflow interrupt, bits et2 (le1.7, enable overflow interrupt) and t2ls1 (tm2con.7, 16-bit overflow interrupt select) must be set. bit t2ov (tm2lr.7) is the timer t2 16-bit overflow flag. all interrupt flags must be reset by software. to enable both byte and 16-bit overflow, t2ls0 and t2ls1 must be set and two interrupt service routines are required. a test on the overflow flags indicates which routine must be executed. for each routine, only the corresponding overflow flag must be cleared. timer t2 may be reset by a rising edge on rt2 (p3.1) if the timer t2 external reset enable bit (t2er) in tm2con is set. this reset also clears the prescaler. in the idle mode, the timer/counter and prescaler are reset and halted. timer t2 is controlled by the tm2con special function register (see section 16.1.1). table 66 timer t2 interrupt enable register ien1 (address e8h) table 67 description of interrupt enable register ien1 bits 76543210 et2 ecan ecm1 ecm0 ect3 ect2 ect1 ect0 bit symbol function 7 et2 enable timer t2 over?w interrupt(s). 6 ecan enable can interrupt. 5 ecm1 enable t2 comparator 1 interrupt. 4 ecm0 enable t2 comparator 0 interrupt. 3 ect3 enable t2 capture register 3 interrupt. 2 ect2 enable t2 capture register 2 interrupt. 1 ect1 enable t2 capture register 1 interrupt. 0 ect0 enable t2 capture register 0 interrupt.
2000 jul 26 114 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 16.1.1 t2 c ontrol r egister (tm2con) table 68 t2 control register (address eah) table 69 description of tm2con bits table 70 timer 2 prescaler select table 71 timer 2 mode select 76543210 t2is1 t2is0 t2er t2bo t2p1 t2p0 t2ms1 t2ms0 bit symbol description 7 t2is1 timer t2 16-bit over?w interrupt select. 6 t2is0 timer t2 byte over?w interrupt select. 5 t2er timer t2 external reset enable. when this bit is set, timer t2 may be reset by a rising edge on rt2 (p3.1). 4 t2bo timer t2 byte over?w interrupt ?g. 3 t2p1 timer t2 prescaler select (see table 70). 2 t2p0 1 t2ms1 timer t2 mode select (see table 71). 0 t2ms0 t2p1 t2p0 timer t2 clock 0 0 clock source 01 1 ? 2 clock source 10 1 ? 4 clock source 11 1 ? 8 clock source t2ms1 t2ms0 mode selected 0 0 timer t2 halted (off) 01 1 ? 6 f clk t2 clock source 1 0 test mode; do not use 1 1 t2 clock source = pin t2
2000 jul 26 115 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 16.1.2 t imer t2 e xtension when a 6 mhz oscillator is used, a 16-bit overflow on timer t2 occurs every 65.5, 131, 262, or 524 ms, depending on the prescaler division ratio; i.e., the maximum cycle time is approximately 0.5 seconds. in applications where cycle times are greater than 0.5 seconds, it is necessary to extend timer t2. this is achieved by selecting f clk /6 as the clock source (set t2ms0, reset t2ms1), setting the prescaler division ration to 1 ? 8 (set t2p0, set t2p1), disabling the byte overflow interrupt (reset t2ls0) and enabling the 16-bit overflow interrupt (set t2ls1). the following software routine is written for a three-byte extension which gives a maximum cycle time of approximately 2400 hours. ovint: push aco ; save accumulator push psw ; save status inc tlmex1 ; increment first byte (low order) of extended timer mov a,tlmex1 jnz intex ; jump to intex if; there is no overflow inc tlmex2 ; increment second byte mov a,tlmex2 jnz intex ; jump to intex if there is no overflow inc tlmex3 ; increment third byte (high order) intex: clr t2ov ; reset interrupt flag pop psw ; restore status pop acc ; restore accumulator reti ; return from interrupt 16.1.3 t imer t2, c apture and c ompare l ogic timer t2 is connected to four 16-bit capture registers and three 16-bit compare registers. a capture register may be used to capture the contents of timer t2 when a transition occurs on its corresponding input pin. a compare register may be used to set or reset port 3 output pins at certain pre-programmable time intervals. the combination of timer t2 and the capture and compare logic is very powerful in applications involving rotating machinery, automotive injection systems, etc. timer t2 and the capture and compare logic are shown in figure 45.
2000 jul 26 116 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.45 block diagram of timer 2. handbook, full pagewidth mhi046 int (1) comp cm0 (s) int (1) comp cm1 (r) comp cm2 ct3i/int5 int (1) cti3 ct3 off f clk t2 rt2 t2er external reset enable prescaler 1/6 t2 counter 8-bit overflow interrupt 16-bit overflow interrupt ct2i/int4 int (1) cti2 ct2 ct1i/int3 int (1) cti1 ct1 ct0i/int2 int (1) cti0 ct0 ste r rte i/o port 3 = set = reset = reserved to internal logic s r * (1) t2 sfr address: tml2 = lower 8 bits tmh2 = higher 8 bits r r r * * * * p3.2 p3.3 p3.4 p3.5 s s s s * * * *
2000 jul 26 117 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 16.1.4 c apture l ogic the four 16-bit capture registers that timer t2 is connected to are: ct0, ct1, ct2, and ct3. these registers are loaded with the contents of timer t2, and an interrupt is requested upon receipt of the input signals ct0l, ct1i, ct2l, or ct3l. these input signals are shared with port 1. the four interrupt flags are in the timer t2 interrupt register (tm2lr special function register). if the capture facility is not required, these inputs can be regarded as additional external interrupt inputs (int2 to int5). using the capture control register ctcon (see section 16.1.4.1), these inputs may capture on a rising edge, a falling edge, or on either a rising or falling edge. the inputs are sampled during s1p1 of each cycle. when a selected edge is detected, the contents of timer t2 are captured at the end of the cycle. 16.1.4.1 capture control register (ctcon) table 72 capture control register (address ebh) table 73 description of ctcon bits 76543210 ctn3 ctp3 ctn2 ctp2 ctn1 ctp1 ctn0 ctp0 bit symbol description 7 ctn3 capture register 3 triggered by a falling edge on ct3l. 6 ctp3 capture register 3 triggered by a rising edge on ct3l. 5 ctn2 capture register 2 triggered by a falling edge on ct2l. 4 ctp2 capture register 2 triggered by a rising edge on ct2l. 3 ctn1 capture register 1 triggered by a falling edge on ct1l. 2 ctp1 capture register 1 triggered by a rising edge on ct1l. 1 ctn0 capture register 0 triggered by a falling edge on ct0l. 0 ctp0 capture register 0 triggered by a rising edge on ct0l. 16.1.5 m easuring t ime i ntervals u sing r egisters when a recurring external event is represented in the form of rising or falling edges on one of the four capture pins, the time between two events can be measured using timer t2 and a capture register. when an event occurs, the contents of timer t2 are copied into the relevant capture register and an interrupt request is generated. the interrupt service routine may then compute the interval time if it knows the previous contents of timer t2 when the last event occurred. with a 6 mhz oscillator, timer t2 can be programmed to overflow every 524 ms. when event interval times are shorter than this, computing the interval time is simple, and the interrupt service routine is short. for longer interval times, the timer t2 extension routine may be used. 16.1.6 c ompare l ogic each time timer t2 is incremented, the contents of the three 16-bit compare registers cm0, cm1, and cm2 are compared with the new counter value of timer t2. when a match is found, the corresponding interrupt flag in tm2lr is set at the end of the following cycle. when a match with cm0 occurs, the controller sets bits 0-3 of port 3 if the corresponding bits of the set enable register ste are at logic 1 (see section 16.1.6.2). when a match with cm1 occurs, the controller resets bits 0-3 of port 3 if the corresponding bits of the reset/enable register rte are at logic 1 (see section 16.1.6.1). if rte is ?? then p3.n is not affected by a match between cm1 or cm2 and timer 2. thus, if the current operation is ?et,?the next operation will be ?eset?even if the port latch is reset by software before the ?eset operation occurs. cm0, cm1, and cm2 are reset by the rst signal. the modified port latch information appears at the port pin during s5p1 of the cycle following the cycle in which a match occurred. if the port is modified by software, the outputs change during s1p1 of the following cycle. each port 3 bit (0-3) can be set or reset by software at any time. a hardware modification resulting from a comparator match takes precedence over a software modification in the same cycle. when the comparator results require a ?et?and a ?eset?at the same time, the port latch will be reset.
2000 jul 26 118 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 16.1.6.1 reset/toggle enable register (rte) table 74 reset/toggle enable register (address efh) table 75 description of rte bits 16.1.6.2 set enable register (ste) table 76 set enable register (address eeh) table 77 description of ste bits 76543210 ???? rp35 rp34 rp33 rp32 bit symbol description 7 to 4 ? reserved. 3 rp35 if high then p3.5 is reset on a match between cm2 and t2. 2 rp34 if high then p3.4 is reset on a match between cm2 and t2. 1 rp33 if high then p3.3 is reset on a match between cm2 and t2. 0 rp32 if high then p3.2 is reset on a match between cm2 and t2. 76543210 ???? sp35 sp34 sp33 sp32 bit symbol description 7 ? reserved. 3 sp35 if high then p3.5 is set on a match between cm2 and t2. 2 sp34 if high then p3.4 is set on a match between cm2 and t2. 1 sp33 if high then p3.3 is set on a match between cm2 and t2. 0 sp32 if high then p3.2 is set on a match between cm2 and t2.
2000 jul 26 119 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 16.1.7 t imer t2 i nterrupt f lag r egister tm2ir seven of the eight timer t2 interrupt flags are located in special function register tm2lr (see section 16.1.7.1). the eights flag is tm2con.4. the ct0l and ct1i flags are set during s4 of the cycle in which the contents of timer t2 are captured. ct0l is scanned by the interrupt logic during s2, and ct1i is scanned during s3. ct2l and ct3l are set during s6 and are scanned during s4 and s5. the associated interrupt requests are recognized during the following cycle. if these flags are polled, a transition at ct0l or ct1i will be recognized one cycle before a transition on ct2l or ct3l since registers are read during s5. the cmi0, cml1 and cml2 flags are set during s6 of the cycle following a match. cml0 is scanned by the interrupt logic during s2; cml1 and cml2 are scanned during s3 and s4. a match of cml0 and cml1 will be recognized by the interrupt logic (or by polling the flags) two cycles after the match takes place. a match of cml2 will cause no interrupt, this flag can be polled only. the 16-bit overflow flag (t2ov) and the byte overflow flag (t2bo) are set during s6 of the cycle in which the overflow occurs. these flags are recognized by the interrupt logic during the next cycle. special function register lp1 (see section 16.1.7.2) is used to determine the timer t2 interrupt priority. setting a bit high gives that function a high priority, and setting a bit low gives the function a low priority. the functions controlled by the various bits of the lp1 register are shown in section 16.1.6.2. 16.1.7.1 interrupt flag register (tm2ir) table 78 interrupt ?g register (address c8h) table 79 description of tm2ir bits 16.1.7.2 interrupt priority register 1 (ip1) table 80 interrupt priority register 1 (address f8h) table 81 description of ip1 bits 76543210 t2ov cmi2/can cmi1 cmi0 cti3 cti2 cti1 cti0 bit symbol description 7 t2ov t2: 16-bit over?w interrupt ?g. 6 cmi2/can cm2: ?g (for polling only). can: can interrupt ?g (polling only). 5 cmi1 cm1: interrupt ?g. 4 cmi0 cm0: interrupt ?g. 3 cti3 ct3: interrupt ?g. 2 cti2 ct2: interrupt ?g. 1 cti1 ct1: interrupt ?g. 0 cti0 ct0: interrupt ?g. 76543210 pt2 pcan pcm1 pcm0 pct3 pct2 pct1 pct0 bit symbol description 7 pt2 t2 over?w interrupt(s) priority level. 6 pcan can interrupt priority level. 5 pcm1 t2 comparator 1 priority interrupt level. 4 pcm0 t2 comparator 0 priority interrupt level. 3 pct3 t2 capture register 3 priority interrupt level. 2 pct2 t2 capture register 2 priority interrupt level. 1 pct1 t2 capture register 1 priority interrupt level. 0 pct0 t2 capture register 0 priority interrupt level.
2000 jul 26 120 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 17 watchdog timer (t3) in addition to timer t2 and the standard timers, a watchdog timer (t3) is also incorporated on the P8XC591. the purpose of a watchdog timer is to reset the microcontroller if it enters erroneous processor states (possibly caused by electrical noise or rfi) within a reasonable period of time. an analogy is the ?ead man? handle?in railway locomotives. when enabled, the watchdog circuitry will generate a system reset if the user program fails to reload the watchdog timer within a specified length of time known as the ?atchdog interval? watchdog circuit description: the watchdog timer (timer t3) consists of an 8-bit timer with an 11-bit prescaler as shown in figure 46. the prescaler is fed with a signal whose frequency is 1 ? 6 the oscillator frequency (1 mhz with a 6 mhz oscillator). the 8-bit timer is incremented every ??seconds, where: t3 is incremented every 1024 s, derived from the oscillator frequency of 12 mhz by the following formula: t = 6 x 2048 x 1/f clk = 1024 s at f clk = 12 mhz. if the 8-bit timer overflows, a short internal reset pulse is generated which will reset the P8XC591. a short output reset pulse is also generated at the rst pin. this short output pulse (3 machine cycles) may be destroyed if the rst pin is connected to a capacitor. this would not, however, affect the internal reset operation. watchdog operation is activated by setting the ?de bit in special function register auxr1. once ?de?is set, it can only be disabled by applying a reset. how to operate the watchdog timer: the watchdog timer has to be reloaded within periods that are shorter than the programmed watchdog interval; otherwise the watchdog timer will overflow and a system reset will be generated. the user program must therefore continually execute sections of code which reload the watchdog timer. the period of time elapsed between execution of these sections of code must never exceed the watchdog interval. when using a 12 mhz oscillator, the watchdog interval is programmable between 1024 s and 261 ms. in order to prepare software for watchdog operation, a programmer should first determine how long his system can sustain an erroneous processor state. the result will be the maximum watchdog interval. as the maximum watchdog interval becomes shorter, it becomes more difficult for the programmer to ensure that the user program always reloads the watchdog timer within the watchdog interval, and thus it becomes more difficult to implement watchdog operation. the programmer must now partition the software in such a way that reloading of the watchdog is carried out in accordance with the above requirements. the programmer must determine in execution times of all software modules. the effect of possible conditional branches, subroutines, external and internal interrupts must all be taken into account. since it may be very difficult to evaluate the execution times of some sections of code, the programmer should use worst case estimations. in any event, the programmer must make sure that the watchdog is not activated during normal operation. the watchdog timer is reloaded in two stages in order to prevent erroneous software from reloading the watchdog. first pcon.4 (wle) must be set. the t3 may be loaded. when t3 is loaded, pcon.4 (wle) is automatically reset. t3 cannot be loaded if pcon.4 (wle) is reset. reload code may be put in a subroutine as it is called frequently. since timer t3 is an up-counter, a reload value of 00h gives the maximum watchdog interval and a reload value of 0ffh gives the minimum watchdog interval. in the idle mode, the watchdog circuitry remains active. when watchdog operation is implemented, the power-down mode cannot be used since both states are contradictory. thus, when watchdog operation is enabled by setting ?de bit in auxr1.4, it is not possible to enter the power-down mode, and an attempt to set the power-down bit (pcon.1) will have no effect. pcon.1 will remain at logic 0. watchdog software example: the following example shows how watchdog operation might be handled in a user program. ; at the program start: t3 equ 0ffh ;address of watchdog timer t3 pcon equ 087h ;address of pcon sfr watch-intv equ 156 ;watchdog interval (e.g., 2 x 100 ms) ;to be inserted at each watchdog location within ;the user program: lcall watchdog ;watchdog service routine: watchdog: orl pcon,#10h ;set condition flag (pcon.4) mov t3,watch-inv ;load t3 with watchdog interval ret if its possible for this subroutine to be called in an erroneous state, then the condition flag wle should be set at different parts of the main program.
2000 jul 26 121 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.46 functional diagram of t3 watchdog timer. (1) see fig.8. handbook, full pagewidth mhi047 internal bus 1/6 f clk write t3 prescaler 11-bit timer t3 (8-bit) load clear to reset circuitry (1) loaden auxr1.4 wde loaden pcon.4 pcon.1 clear wle pd internal bus
2000 jul 26 122 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 18 pulse width modulated outputs the P8XC591 contains two pulse width modulated (pwm) output channels (see fig.47). these channels generate pulses of programmable length and interval. the repetition frequency is defined by an 8-bit prescaler pwmp, which supplies the clock for the counter. the prescaler and counter are common to both pwm channels. the 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. the value of the 8-bit counter is compared to the contents of two registers: pwm0 and pwm1. provided the contents of either of these registers is greater than the counter value, the corresponding pwm0 or pwm1 output is set low. if the contents of these registers are equal to, or less than the counter value, the output will be high. the pulse-width-ratio is therefore defined by the contents of the registers pwm0 and pwm1. the pulse-width-ratio is in the range of 0 ? 255 to 255 ? 255 and may be programmed in increments of 1 ? 255 . buffered pwm outputs may be used to drive dc motors. the rotation speed of the motor would be proportional to the contents of pwmn. the pwm outputs may also be configured as a dual dac. in this application, the pwm outputs must be integrated using conventional operational amplifier circuitry. if the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the pwm outputs before they are integrated. the repetition frequency f pwm , at the pwmn outputs is given by: this gives a repetition frequency range of 184 hz to 47 khz (at f clk = 12 mhz). by loading the pwm registers with either 00h or ffh, the pwm channels will output a constant high or low level, respectively. since the 8-bit counter counts modulo 255, it can never actually reach the value of the pwm registers when they are loaded with ffh. when a compare register (pwm0 or pwm1) is loaded with a new value, the associated output is updated immediately. it does not have to wait until the end of the current counter period. both pwmn output pins are driven by push-pull drivers. these pins are not used for any other purpose. f pwm f clk pwmp 1 + () 255 --------------------------------------------------- - = fig.47 functional diagram of pulse width modulated outputs. handbook, full pagewidth mhi048 f clk pwmp pwm1 prescaler 8-bit counter pwm0 internal bus 8-bit comparator 8-bit comparator output buffer pwm1 output buffer pwm0
2000 jul 26 123 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 18.1 prescaler frequency control register (pwmp) reading pwmp gives the current reload value. the actual count of the prescaler cannot be read. table 82 prescaler frequency control register (address feh), reset value = 00h table 83 description of pwmp bits 18.2 pulse width register 0 (pwm0) table 84 pulse width register (address fch), reset value = 00h table 85 description of pwm0 bits 18.3 pulse width register 1 (pwm1) table 86 pulse width register (address fdh) table 87 description of pwm1 bits 76543210 pwmp.7 pwmp.6 pwmp.5 pwmp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 bit symbol description 7 to 0 pwmp.7 to pwmp.0 prescaler division factor . the prescaler division factor = (pwmp) + 1. 76543210 pwm0.7 pwm0.6 pwm0.5 pwm0.4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 bit symbol description 7 to 0 pwm0.7 to pwm0.0 pulse width ratio. 76543210 pwm1.7 pwm1.6 pwm1.5 pwm1.4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 bit symbol description 7 to 0 pwm1.7 to pwm1.0 pulse width ratio. low/high ratio of pwm0 signals pwm0 () 255 pwm0 () --------------------------------------- - = low/high ratio of pwm1 signals pwm1 () 255 pwm1 () --------------------------------------- - =
2000 jul 26 124 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 19 port 1 operation port 1 may be used to input up to 6 analog signals adc. unused adc inputs may be used to input digital inputs. these inputs have an inherent hysteresis to prevent the input logic from drawing excessive current from the power lines when driven by analog signals. channel to channel crosstalk (ct) should be taken into consideration when both analog and digital signals are simultaneously input to port 3 (see chapter 24 ?c characteristics?. 20 analog-to-digital converter (adc) 20.1 adc features ? 10-bit resolution ? 6 multiplexed analog inputs ? start of a conversion by software or with an external signal ? conversion time for one 10-bit analog-to-digital conversion: 25 s @ 12 mhz ? differential non-linearity (dl e ): 1 lsb ? integral non-linearity (il e ): 2 lsb ? offset error (os e ): 2 lsb ? gain error (g e ): 4% ? absolute voltage error (a e ): 3 lsb ? channel-to-channel matching (m ctc ): 1 lsb ? crosstalk between analog inputs (c t ): < 60 db at 100 khz ? monotonic and no missing codes ? separated analog (v ssa ) and digital (v dd ,v ss ) supply voltages ? reference voltage special pin: v ref(p)(a) . for information on the adc characteristics, refer to chapter 24. 20.2 adc functional description the analog input circuitry consists of an 6-input analog multiplexer and a 10-bit, straight binary, successive approximation adc. the a/d can also be operated in 8-bit mode with faster conversion times by setting bit adc8 (auxr1.7). the 8-bit result will be contained in the adch register. the analog reference voltage and analog power supplies are connected via separate input pins. for 10-bit accuracy, the conversion takes 50 machine cycles, i.e., 25 s at an oscillator frequency of 12 mhz. for the 8-bit mode, the conversion takes 24 machine cycles. input voltage swing is from 0 v to +5 v. because the internal dac employs a ratiometric potentiometer, there are no discontinouties in the converter characteristic. figure 48 shows a functional diagram of the analog input circuitry. the adc has the option of either being powered off in idle mode for reduced power consumption or being active in the idle mode for reducing internal noise during the conversion. this option is selected by the aidl bit of auxr1 register (auxr1.6). with the aidl bit set, the adc is active in the idle mode, and with the aidl bit cleared, the adc is powered off in idle mode.
2000 jul 26 125 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.48 functional diagram of analog input circuitry. handbook, full pagewidth mhi050 internal bus analog input multiplexer adc0 adc1 adc2 adc3 adc4 adc5 analog ground analog ref. + n.c. n.c. 12 0 4567 3 10-bit a/d converter 12 0 4567 adch adcon 3 20.3 10-bit analog-to-digital conversion figure 48 shows the elements of a successive approximation (sa) adc. the adc contains a dac which converts of a successive approximation register to a voltage (vdac) which is compared to the analog input voltage (v in ). the output of the comparator is fed to the successive approximation control logic which controls the successive approximation register. a conversion is initiated by setting adcs in adcon register. adcs can bet set by software only. the software start mode is selected when control bit adcon.5 (adex) = 0. a conversion is then started by setting control bit adcon.3 (adcs). the software start mode is selected when adcon.5 = 1, and a conversion may be started by setting adcon.3. when a conversion is initiated, the conversion starts at the beginning of the machine cycle which follows the instruction that sets adcs. adcs is actually implemented with two flip-flops; a command flip-flop which is affected by set operations, and a status flag which is accessed during read operations. the next two machine cycles are used to initiate the converter. at the end of the first cycle, the adcs status flag is set and a value of ??will be returned if the adcs flag is read while the conversion is progress. sampling of the analog input commences at the end of the second cycle. during the next eight machine cycles, the voltage at the previously selected pin of port 1 is sampled, and this input voltage should be stable in order to obtain a useful sample. in any event, the input voltage slew rate must be less than 10 v/ms in order to prevent an undefined result. the successive approximation control logic first sets the most significant bit and clears all other bits in the successive approximation register (10 0000 0000b). the output of the dac (50% full scale) is compared to the input voltage v in . if the input voltage is greater than vdac, then the bit remains set; otherwise it is cleared. the successive approximation control logic now sets the next most significant bit (11 0000 0000b or 01 0000 0000b, depending on the previous result), and vdac is compared to v in again. if the input voltage is greater than vdac, then the bit being tested remains set;
2000 jul 26 126 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 otherwise the bit being tested is cleared. this process is repeated until all ten bits have been tested, at which stage the result of the conversion is held in the successive approximation register. figure 48 shows a conversion flow chart. the bit pointer identifies the bit under test. the conversion takes four machine cycles per bit. the end of the 10-bit conversion is flagged by control bit adcon.4 (adci). the upper 8 bits of the result are held in special function register adch, and the two remaining bits are held in adcon.7 (adc.1) and adcon.6 (adc.0). the user may ignore the two least significant bits in adcon and use the adc as an 8-bit converter (8 upper bits in adch). in any event, the total actual conversion time is 50 machine cycles for the P8XC591. adci will be set and the adcs status flag will be reset 50 (or 24) cycles after the command flip-flop (adcs) is set. control bits adcon.0, adcon.1, and adcon.2 are used to control an analog multiplexer which selects one of six analog channels (see section 20.3.1). an adc conversion in progress is unaffected by a new software adc start. the result of a completed conversion remains unaffected provided adci = logic 1; a new adc conversion already in progress is aborted when the idle or power-down mode is entered. the result of a completed conversion (adci = logic 1) remains unaffected when entering the idle mode. fig.49 successive approximation adc. handbook, full pagewidth mhi051 successive approximation register dac successive approximation control logic start stop v in v dac full scale t/tau v dac 1/2 3/4 7/8 15/16 29/32 59/64 1 1 0 2 3456 v in
2000 jul 26 127 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.50 a/d conversion flowchart. handbook, full pagewidth mhi052 reset sar soc [ bit pointer ] = msb conversion time test complete [ bit ] n = 1 [ bit ] n = 0 10 [ bit pointer ] + 1 end end end of conversion start of conversion eoc test bit pointer
2000 jul 26 128 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 20.3.1 adc c ontrol r egister (adcon) table 88 adc control register (address c5h); reset value = xx00 0000b table 89 description of adcon bits table 90 adc status table 91 selected analog channel 76543210 adc.1 adc.0 adex adci adcs aadr2 aadr1 aadr0 bit symbol description 7 adc.1 bit 1 of adc result. 6 adc.0 bit 0 of adc result. 5 ? reserved for future use. 4 adci adc interrupt ?g. this ?g is set when an a/d conversion result is ready to be read. an interrupt is invoked if its is enabled. the ?g may be cleared by the interrupt service routine. while this ?g is set, the adc cannot start a new conversion. adci cannot be set by software. 3 adcs adc start and status. setting this bit starts an a/d conversion. it is set by software. the adc logic ensures that this signal is high while the adc is busy. on completion of the conversion. adcs is reset immediately after the interrupt ?g has been set. adcs cannot be reset by software. a new conversion may not be started while either adcs or adci is high (see table 90). if addci is cleared by software while adcs is set at the same time, a new a/d conversion with the same channel number may be started. but it is recommended to reset adci before adcs is set. 2 to 0 aadr2 to aadr0 analogue input select: this binary coded address selects one of the six analogue port bits of p1 to be input to the converter. it can only be changed when adci and adcs are both low. adci adcs adc status 0 0 adc not busy; a conversion can be started 0 1 adc busy; start of a new conversion is blocked 1 0 conversion completed; start of a new conversion requires adci=0 1 1 conversion completed; start of a new conversion requires adci=0 aadr2 aadr1 aadr0 selected analog channel 0 0 0 adc0 (p1.2) 0 0 1 adc1 (p1.3) 0 1 0 adc2 (p1.4) 0 1 1 adc3 (p1.5) 1 0 0 adc4 (p1.6) 1 0 1 adc5 (p1.7)
2000 jul 26 129 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 20.4 10-bit adc resolution and analog supply figure 48 shows how the adc is realized. the adc has its own analog ground (av ss ) and a positive analog reference pin (v ref+ ) connected to each end of the dac? resistance-ladder. the ladder has 1023 equally spaced taps, separated by a resistance of ?? the first tap is located 0.5 x r above av ss , and the last tap is located 1.5 x r below v ref+ . this gives a total ladder resistance of 1024 x r. this structure ensures that the dac is monotonic and results in a symmetrical quantization error is shown in figure 48. for input voltages between 0 v and + 1/2 lsb, the 10-bit result of an a/d conversion will be 00 0000 0000b = 0000h. for input voltages between (v ref+ ) - 3/2 lsb and v ref+ , the result of a conversion will be 11 1111 1111b = 3fffh. av ref+ may be between v dd +0.2 v and av ss - 0.2 v. av ref+ should be positive 0 v and av ref+ . if the analog input voltage range is from 2 v to 4 v, the 10-bit resolution can be obtained over this range if av ref+ = 4 v. the result can always can always be calculated from the following formula: result = 1024 v in av ref+ ---------------- 20.5 power reduction modes the P8XC591 has two reduced power modes of operation: the idle mode and the power-down mode. these modes are entered by setting bits in the pcon special function register. when the P8XC591 enters the idle mode, the following functions are disabled: cpu (halted) timer t2 (halted and reset) pwm0, pwm1 (reset; outputs are high) adc (may be enabled for operation in idle mode by setting bit aidc (auxr1.6). in idle mode, the following functions remain active: timer 0 timer 1 timer t3 sio0 sio1 external interrupts when the P8XC591 enters the power-down mode, the oscillator is stopped. the power-down mode is entered by setting the pd bit in the pcon register. the pd bit can only be set if the ?de?bit is 0. fig.51 adc realization. value 0000 0000 00 is output for voltages 0 v + 1 ? 2 lsb value 1111 1111 11 is output for voltages (v ref+ 3 ? 2 lsb) to v ref+ handbook, full pagewidth mhi053 r/2 av ref + r r r r r/2 av ss v in v ref total resistance = 1023r + 2 r/ = 1024r comparator decoder start lsb msb successive approximation register successive approximation control logic ready 1021 1022 1023 1 0 2 3
2000 jul 26 130 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.52 a/d input: equivalent circuit. handbook, full pagewidth mhi054 multiplexer rm n + 1 rm n sm n + 1 c c c s i n + 1 i n sm n r s + v analog input to comparator rm = 0.5 - 3 k ? c s + c c = 15 pf maximum r s = recommended < 9.6 k ? for 1 lsb @ 12 mhz note: because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. when a conversion is initiated, switch sm closes for 8 t cy (4 s @ 12 mhz crystal frequency) during which time capacitance c s +c c is changed. it should be noted that the sampling causes the analog input to prevent a varying load to an analog source. fig.53 effective conversion characteristic. handbook, full pagewidth mhi055 101 100 011 010 001 000 0q q = lsb = 5 mv + q/2 ? q/2 2q 3q 4q 5q v in v in v in ? v digital code out quantization error symmetrical quantization error
2000 jul 26 131 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 21 interrupts the 8xc591 has fifteen interrupt sources, each of which can be assigned one of four priority levels. the five interrupt sources common to the 80c51 are the external interrupts ( int0 and int1), the timer 0 and timer 1 interrupts (lt0 and it1), and the serial i/o interrupt (ri or ti). in the 8xc591, the standard serial interrupt is called sio0. the seven timer t2 interrupts are generated by flags ctl0-cti3, cml0-cml1, and by the logical or of flags t2ov and t2bo. flags ctl0 to cti3 are set by input signals ct0l to ct3i. the inputs int2 to int5 can be regarded as 4 additional external interrupts, if the capture facility of timer t2 is not used (details see timer t2 in section 16.1.4.1). flags cml0 to cml1 are set when a match occurs between timer t2 and the compare registers cm0 and cm1. when an 8-bit or 16-bit overflow occurs, flags t2bo and t2ov are set, respectively. these eight flags are not cleared by hardware and must be reset by software to avoid recurring interrupts. the adc interrupt is generated by the adcl flag in the adc control register (adcon). this flag is set when an adc conversion result is ready to be read. adcl is not cleared by hardware and must be reset by software to avoid recurring interrupts. the sio1 (i 2 c) interrupt is generated by the si flag in the si01 control register (s1con). this flag is set when s1sta is loaded with a valid status code. the adcl flag may be reset by software. it cannot be set by software. all other flags that generate interrupts may be set or cleared by software, and the effect is the same as setting or resetting the flags by hardware. thus, interrupts may be generated by software and pending interrupts can be cancelled by software. a can interrupt is generated (vector address 006bh) when one or more bits of cancon register are set (refer to can section 12.5.5 interrupt register (ir) for details). 21.1 interrupt enable registers each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable special function registers leno and len1. all interrupt sources can also be globally enabled or disabled by setting or clearing bit ea in leno. the interrupt enable registers are described in section 21.2.1 and 21.2.2). there are 3 sfrs associated with each of the four-level interrupts. they are the lenx, lpx, and lpxh (see section 21.2.3 to 21.2.6). the lpxh (interrupt priority high) register makes the four-level interrupt structure possible. the function of the lpxh sfr is simple and when combined with the lpx sfr determines the priority of each interrupt. the priority of each interrupt is determined as shown in the following table: table 92 interrupt priority register the priority scheme for servicing the interrupts is the same as that for the 80c51, except there are four interrupt levels rather than two as on the 80c51. an interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. if an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. if a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. when the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. priority bits interrupt priority level ipxh.x ipx.x 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority)
2000 jul 26 132 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 21.2 interrupt enable and priority registers 21.2.1 i nterrupt e nable r egister 0 (ien0) logic 0 = interrupt disabled; logic 1 = interrupt enabled. table 93 interrupt enable register 0 (address a8h) table 94 description of ien0 bits 21.2.2 i nterrupt e nable r egister 1 (ien1) logic 0 = interrupt disabled; logic 1 = interrupt enabled. table 95 interrupt enable register 1 (address e8h) table 96 description of ien1 bits 76543210 ea ead es1 es0 et1 ex1 et0 ex0 bit symbol description 7ea global enable/disable control . if bit ea is: low, then no interrupt is enabled. high, then any individually enabled interrupt will be accepted. 6 ead enable adc interrupt. 5 es1 enable sio1 (i 2 c) interrupt. 4 es0 enable sio0 (uart) interrupt. 3 et1 enable timer 1 interrupt. 2 ex1 enable external 1 interrupt / seconds interrupt. 1 et0 enable timer 0 interrupt. 0 ex0 enable external 0 interrupt. 76543210 et2 ecan ecm1 ecm0 ect3 ect2 ect1 ect0 bit symbol description 7 et2 enable t2 over?w interrupt(s). 6 ecan enable can interrupt. 5 ecm1 enable t2 comparator 1 interrupt. 4 ecm0 enable t2 comparator 0 interrupt. 3 ect3 enable t2 capture register 3 interrupt. 2 ect1 enable t2 capture register 2 interrupt. 1 ect1 enable t2 capture register 1 interrupt. 0 ect0 enable t2 capture register 0 interrupt.
2000 jul 26 133 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 21.2.3 i nterrupt p riority r egister 0 (ip0) logic 0 = low priority; logi c 1 = high priority. table 97 interrupt priority register 0 (address b8h) table 98 description of ip0 bits 21.2.4 i nterrupt p riority h igh r egister 0 (ip0h) logic 0 = low priority; logi c 1 = high priority. table 99 interrupt priority high register 0 (address b7h) table 100 description of ip0h bits 76543210 ? pad ps1 ps0 pt1 px1 pt0 px0 bit symbol description 7 ? reserved for future use. 6 pad adc interrupt priority level. 5 ps1 sio1 (i 2 c) interrupt priority level. 4 ps0 sio0 (uart) interrupt priority level. 3 pt1 timer 1 interrupt priority level. 2 px1 external interrupt 1/seconds priority level. 1 pt0 timer 0 interrupt priority level. 0 px0 external interrupt 0 priority level. 76543210 ? padh ps1h ps0h pt1h px1h pt0h px0h bit symbol description 7 ? reserved for future use. 6 padh adc interrupt priority level. 5 ps1h sio1 (i 2 c) interrupt priority level. 4 ps0h sio0 (uart) interrupt priority level. 3 pt1h timer 1 interrupt priority level. 2 px1h external interrupt 1/seconds priority level. 1 pt0h timer 0 interrupt priority level. 0 px0h external interrupt 0 priority level.
2000 jul 26 134 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 21.2.5 i nterrupt p riority r egister 1 (ip1) logic 0 = low priority; logi c 1 = high priority. table 101 interrupt priority register 1 (address f8h) table 102 description of ip1 bits 21.2.6 i nterrupt p riority r egister h igh 1 (ip1h) logic 0 = low priority; logi c 1 = high priority. table 103 interrupt priority register high 1 (address f7h) table 104 description of ip1h bits 76543210 pt2 pcan pcm1 pcm0 pct3 pct2 pct1 pct0 bit symbol description 7 pt2 t2 over?w interrupt(s) priority level. 6 pcan can interrupt priority level. 5 pcm1 t2 comparator 1 interrupt priority level. 4 pcm0 t2 comparator 0 interrupt priority level. 3 pct3 t2 capture register 3 interrupt priority level. 2 pct2 t2 capture register 2 interrupt priority level. 1 pct1 t2 capture register 1 interrupt priority level. 0 pct0 t2 capture register 0 interrupt priority level. 76543210 pt2 pcanh pcm1h pcm0h pct3h pct2h pct1h pct0h bit symbol description 7 pt2 t2 over?w interrupt(s) priority level. 6 pcanh can interrupt priority level high. 5 pcm1h t2 comparator 1 interrupt priority level. 4 pcm0h t2 comparator 0 interrupt priority level. 3 pct3h t2 capture register 3 interrupt priority level. 2 pct2h t2 capture register 2 interrupt priority level. 1 pct1h t2 capture register 1 interrupt priority level. 0 pct0h t2 capture register 0 interrupt priority level.
2000 jul 26 135 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 21.3 interrupt priority table 105 interrupt priority structure source symbol priority within level external interrupt 0 x0 (highest) sio1 (i 2 c) s1 adc completion adc timer 0 over?w t0 t2 capture 0 ct0 t2 compare 0 cm0 external interrupt 1 x1 t2 capture 1 ct1 t2 compare 1 cm1 timer 1 over?w t1 t2 capture 2 ct2 can can serial i/o 0 (uart) s0 t2 compare 3 ct3 timer t2 over?w t2 (lowest) 21.4 interrupt vectors the vector indicates the program memory location where the appropriate interrupt service routine starts (see table 106). table 106 interrupt vector addresses source symbol vector external interrupt 0 x0 0003h timer 0 over?w t0 000bh external interrupt 1 x1 0013h timer 1 over?w t1 001bh serial i/o 0 (uart) s0 0023h sio1 (i 2 c) s1 002bh t2 capture 0 ct0 0033h t2 capture 1 ct1 003bh t2 capture 2 ct2 0043h t2 capture 3 ct3 004bh adc completion adc 0053h t2 compare 0 cm0 005bh t2 compare 1 cm1 0063h can interrupt can 006bh t2 over?w t2 0073h
2000 jul 26 136 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 22 instruction set for the description of the data addressing modes and hexadecimal opcode cross-reference see table 111. table 107 instruction set description: arithmetic operations mnemonic description bytes cycles opcode (hex) arithmetic operations add a,rr add register to a 1 1 2* add a,direct add direct byte to a 2 1 25 add a,@ri add indirect ram to a 1 1 26, 27 add a,#data add immediate data to a 2 1 24 addc a,rr add register to a with carry ?g 1 1 3* addc a,direct add direct byte to a with carry ?g 2 1 35 addc a,@ri add indirect ram to a with carry ?g 1 1 36, 37 addc a,#data add immediate data to a with carry ?g 2 1 34 subb a,rr subtract register from a with borrow 1 1 9* subb a,direct subtract direct byte from a with borrow 2 1 95 subb a,@ri subtract indirect ram from a with borrow 1 1 96, 97 subb a,#data subtract immediate data from a with borrow 2 1 94 inc a increment a 1 1 04 inc rr increment register 1 1 0* inc direct increment direct byte 2 1 05 inc @ri increment indirect ram 1 1 06, 07 dec a decrement a 1 1 14 dec rr decrement register 1 1 1* dec direct decrement direct byte 2 1 15 dec @ri decrement indirect ram 1 1 16, 17 inc dptr increment data pointer 1 2 a3 mul ab multiply a and b 1 4 a4 div ab divide a by b 1 4 84 da a decimal adjust a 1 1 d4
2000 jul 26 137 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 108 instruction set description: logic operations mnemonic description bytes cycles opcode (hex) logic operations anl a,rr and register to a 1 1 5* anl a,direct and direct byte to a 2 1 55 anl a,@ri and indirect ram to a 1 1 56, 57 anl a,#data and immediate data to a 2 1 54 anl direct,a and a to direct byte 2 1 52 anl direct,#data and immediate data to direct byte 3 2 53 orl a,rr or register to a 1 1 4* orl a,direct or direct byte to a 2 1 45 orl a,@ri or indirect ram to a 1 1 46, 47 orl a,#data or immediate data to a 2 1 44 orl direct,a or a to direct byte 2 1 42 orl direct,#data or immediate data to direct byte 3 2 43 xrl a,rr exclusive-or register to a 1 1 6* xrl a,direct exclusive-or direct byte to a 2 1 65 xrl a,@ri exclusive-or indirect ram to a 1 1 66, 67 xrl a,#data exclusive-or immediate data to a 2 1 64 xrl direct,a exclusive-or a to direct byte 2 1 62 xrl direct,#data exclusive-or immediate data to direct byte 3 2 63 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 rl a rotate a left 1 1 23 rlc a rotate a left through the carry ?g 1 1 33 rr a rotate a right 1 1 03 rrc a rotate a right through the carry ?g 1 1 13 swap a swap nibbles within a 1 1 c4
2000 jul 26 138 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 109 instruction set description: data transfer note 1. mov a,acc is not permitted. mnemonic description bytes cycles opcode (hex) data transfer mov a,rr move register to a 1 1 e* mov a,direct (note 1) move direct byte to a 2 1 e5 mov a,@ri move indirect ram to a 1 1 e6, e7 mov a,#data move immediate data to a 2 1 74 mov rr,a move a to register 1 1 f* mov rr,direct move direct byte to register 2 2 a* mov rr,#data move immediate data to register 2 1 7* mov direct,a move a to direct byte 2 1 f5 mov direct,rr move register to direct byte 2 2 8* mov direct,direct move direct byte to direct 3 2 85 mov direct,@ri move indirect ram to direct byte 2 2 86, 87 mov direct,#data move immediate data to direct byte 3 2 75 mov @ri,a move a to indirect ram 1 1 f6, f7 mov @ri,direct move direct byte to indirect ram 2 2 a6, a7 mov @ri,#data move immediate data to indirect ram 2 1 76, 77 mov dptr,#data 16 load data pointer with a 16-bit constant 3 2 90 movc a,@a+dptr move code byte relative to dptr to a 1 2 93 movc a,@a+pc move code byte relative to pc to a 1 2 83 movx a,@ri move external ram (8-bit address) to a 1 2 e2, e3 movx a,@dptr move external ram (16-bit address) to a 1 2 e0 movx @ri,a move a to external ram (8-bit address) 1 2 f2, f3 movx @dptr,a move a to external ram (16-bit address) 1 2 f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a,rr exchange register with a 1 1 c* xch a,direct exchange direct byte with a 2 1 c5 xch a,@ri exchange indirect ram with a 1 1 c6, c7 xchd a,@ri exchange low-order digit indirect ram with a 1 1 d6, d7
2000 jul 26 139 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 110 instruction set description: boolean variable manipulation, program and machine control mnemonic description bytes cycles opcode (hex) boolean variable manipulation clr c clear carry ?g 1 1 c3 clr bit clear direct bit 2 1 c2 setb c set carry ?g 1 1 d3 setb bit set direct bit 2 1 d2 cpl c complement carry ?g 1 1 b3 cpl bit complement direct bit 2 1 b2 anl c,bit and direct bit to carry ?g 2 2 82 anl c,/bit and complement of direct bit to carry ?g 2 2 b0 orl c,bit or direct bit to carry ?g 2 2 72 orl c,/bit or complement of direct bit to carry ?g 2 2 a0 mov c,bit move direct bit to carry ?g 2 1 a2 mov bit,c move carry ?g to direct bit 2 2 92 program and machine control acall addr11 absolute subroutine call 2 2 ? 1 lcall addr16 long subroutine call 3 2 12 ret return from subroutine 1 2 22 reti return from interrupt 1 2 32 ajmp addr11 absolute jump 2 2 ? 1 ljmp addr16 long jump 3 2 02 sjmp rel short jump (relative address) 2 2 80 jmp @a+dptr jump indirect relative to the dptr 1 2 73 jz rel jump if a is zero 2 2 60 jnz rel jump if a is not zero 2 2 70 jc rel jump if carry ?g is set 2 2 40 jnc rel jump if carry ?g is not set 2 2 50 jb bit,rel jump if direct bit is set 3 2 20 jnb bit,rel jump if direct bit is not set 3 2 30 jbc bit,rel jump if direct bit is set and clear bit 3 2 10 cjne a,direct,rel compare direct to a and jump if not equal 3 2 b5 cjne a,#data,rel compare immediate to a and jump if not equal 3 2 b4 cjne rr,#data,rel compare immediate to register and jump if not equal 3 2 b* cjne @ri,#data,rel compare immediate to indirect and jump if not equal 3 2 b6, b7 djnz rr,rel decrement register and jump if not zero 2 2 d* djnz direct,rel decrement direct and jump if not zero 3 2 d5 nop no operation 1 1 00
2000 jul 26 140 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 table 111 description of the mnemonics in the instruction set mnemonic description data addressing modes rr working register r0-r7. direct 128 internal ram locations and any special function register (sfr). @ri indirect internal ram location addressed by register r0 or r1 of the actual register bank. #data 8-bit constant included in instruction. #data 16 16-bit constant included as bytes 2 and 3 of instruction. bit direct addressed bit in internal ram or sfr. addr16 16-bit destination address. used by lcall and ljmp. the branch will be anywhere within the 64 kbytes program memory address space. addr11 11-bit destination address. used by acall and ajmp. the branch will be within the same 2 kbytes page of program memory as the ?st byte of the following instruction. rel signed (two's complement) 8-bit offset byte. used by sjmp and all conditional jumps. range is ? 128 to +127 bytes relative to ?st byte of the following instruction. hexadecimal opcode cross-reference * 8, 9, a, b, c, d, e, f. ? 1, 3, 5, 7, 9, b, d, f. ? 0, 2, 4, 6, 8, a, c, e. 22.1 addressing modes most instructions have a ?estination, source?field that specifies the data type, addressing modes and operands involved. for all these instructions, except for movs, the destination operand is also the source operand (e.g. add a,r7). there are five kinds of addressing modes: ? register addressing r0 - r7 (4 banks) a,b,c (bit), ab (2 bytes), dptr (double byte) ? direct addressing lower 128 bytes of internal main ram (including the 4 r0-r7 register banks) special function registers 128 bits in a subset of the internal main ram 128 bits in a subset of the special function registers ? register-indirect addressing internal main ram (@r0, @r1, @sp [push/pop]) internal auxiliary ram (@r0, @r1, @dptr) external data memory (@r0, @r1, @dptr) ? immediate addressing program memory (in-code 8 bit or 16 bit constant) ? base-register-plus-index-register-indirect addressing program memory look-up table (@dptr+a, @pc+a) the first three addressing modes are usable for destination operands.
2000 jul 26 141 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 23 limiting values in accordance with the absolute maximum rating system (iec 134); note 1 notes 1. the following applies to the absolute maximum ratings: a) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the chapters 24 and 25 of this specification is not implied. b) this product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge. however, its suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package, not on device power consumption. symbol parameter min. max. unit v dd voltage on v dd to v ss and scl, sda to v ss ? 0.5 +6.5 v v i input voltage on any other pin to v ss ? 0.5 v dd + 0.5 v i i , i o input/output current on any i/o pin ? 5ma p tot total power dissipation (note 2) ? 1.0 w t stg storage temperature range ? 65 +150 c t amb operating ambient temperature range: P8XC591vfx ? 40 +85 c v pp voltage on ea/v pp to v ss ? 0.5 +13 v
2000 jul 26 142 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 24 dc characteristics v dd =5v 5%; v ss = 0 v; all voltages with respect to v ss unless otherwise speci?d; t amb = ? 40 to +85 c for the P8XC591vfx ; v dd = 5 v 5%; v ss =0v; av ss = 0 v. symbol parameter conditions min. max. unit supply i dd operating supply current t clk = 12 mhz see notes 2 and 3 45 ma i id supply current idle mode t clk = 12 mhz see notes 2 and 4 ? 25 ma i pd supply current power-down mode 2 v < v pd 2000 jul 26 143 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 outputs v ol low level output voltage ports 1, 2, 3 (except p1.0, p1.6, p1.7) i ol = 1.6 ma; see note 8 0.4 v v ol1 low level output voltage port 0, ale, psen, rst, pwm0, pwm1 i ol = 3.2; see note 8 0.4 v v ol2 low level output voltage p1.6, p1.7 i ol = 3.0 ma; see note 8 ? 0.4 v v ol3 low level output voltage p1.0 and p1.1 i ol = 8.0 ma ? 0.3 v dd v v oh high level output voltage ports 1, 2, 3 in pseudo-bidirectional output mode (except p1.1, p1.6 and p1.7 i oh = -60 a 2.4 v v oh1 high level output voltage port 0 and port 2 in external bus mode, port 2 in push-pull mode, ale, psen, pwm0, pwm1 i oh = ? 3.2 ma; see note 9 v dd ? 0.7 v v oh2 high level output voltage, p1.0 and p1.1 i oh = ? 1.6 ma 0.7 v dd v v oh3 high level output voltage, ports 1, 2, 3 in push-pull output mode (except p1.0, p1.1, p1.6, p1.7) i oh = ? 1.6 ma v dd ? 0.7 v r rst rst pull-up resistor 40 225 k ? c i/o i/o pin capacitance test frequency = 1 mhz; t amb =25 c ? 15 pf analog inputs av in analog input voltage av ss ? 0.2 v dd + 0.2 v av ref+ reference voltage ? v dd + 0.2 v r ref resistance between av ref+ and av ss 10 50 k ? c ia analog input capacitance ? 15 pf t ads sampling time ? 5 tcy; note 1 8 tcy s s t adc conversion time (including sampling time) ? 24 tcy; note 1 50 tcy s s dl e differential non-linearity see notes 10, 11, 12 ? 1 lsb il e8 integral non-linearity (8-bit mode) ? 1; note 1 lsb il e integral non-linearity see notes 10, 13 ? 2 lsb os e8 offset error (8-bit mode) ? 1; note 1 lsb os e offset error see notes 10, 15 ? 2 lsb g e gain error ? 0.4 % a e absolute voltage error see notes 10, 16 ? 3 lsb m ctc channel-to-channel matching ? 1 lsb c t crosstalk between analog inputs of port 1 0 to 100 khz; see notes 17, 18 ?? 60 db symbol parameter conditions min. max. unit
2000 jul 26 144 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 notes to the dc characteristics 1. 8-bit mode 2. see figures 62 through 64 for i dd test conditions. 3. the operating supply current is measured with all output pins disconnected; xtal1 driven with t r =t f = 10 ns; v il =v ss + 0.5 v; v ih =v dd ? 0.5 v; xtal2 not connected; ea = port 0 = v dd ; = rst=v ss . 4. the idle mode supply current is measured with all output pins disconnected; xtal1 driven with t r =t f = 10 ns; v il =v ss + 0.5 v; v ih =v dd ? 0.5 v; xtal2 not connected; port 0 = rst = v dd ; ea = v ss . 5. the power-down current is measured with all output pins disconnected; xtal2 not connected; rst = port 0 = v dd ; ea = xtal1 = v ss . 6. the input threshold voltage of p1.6 and p1.7 (sio1) meets the i 2 c specification, so an input voltage below 1.5 v will be recognized as a logic 0 while an input voltage above 3.0 v will be recognized as a logic 1. 7. pins of port 1 (except p1.6, p1.7), 2 and 3 source a transition current when they are being externally driven from high to low. the transition current reaches its maximum value when v in is approximately 2 v. 8. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make high-to-low transitions during bus operations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single outputs sinks more than 5 ma and no more than two outputs exceed in the test conditions. 9. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v dd specification when the address bits are stabilizing. 10. conditions: av ss = 0 v; v dd = 5.0 v. measurement by continuous conversion of av in = ? 20 mv to 5.12 v in steps of 0.5 mv, derivating parameters from collected conversion results of adc. av ref+ (P8XC591) = 4.977 v, adc is monotonic with not missing codes. 11. the differential non-linearity (d le ) is the difference between the actual step width and the ideal step width (see fig.54). 12. the adc is monotonic; there are no missing codes. 13. the integral non-linearity (i le ) is the peak difference between the centre of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error (see fig.54). 14. the offset error (os e ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve (see fig.54). 15. the gain error (g e ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. gain error is constant at every point on the transfer curve (see fig.54). 16. the absolute voltage error (a e ) is the maximum difference between the centre of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. 17. this should be considered when both analog and digital signals are simultaneously input to port 1. 18. the parameter is guaranteed by design and characterized, but is not production tested.
2000 jul 26 145 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.54 adc conversion characteristic. (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential non-linearity (dl e ). (4) integral non-linearity (il e ). (5) centre of a step of the actual transfer curve. handbook, full pagewidth mgd634 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 v in(a) (lsb ideal ) code out offset error os e offset error os e gain error g e (2) (3) (4) (5) (1) 1 lsb (ideal) 1lsb ideal av ref+ 1024 ------------------- - =
2000 jul 26 146 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 25 ac characteristics v dd =5v 5%; v ss =0v; t amb = ? 40 c to +85 c; c l = 100 pf for port 0, ale and psen; c l = 80 pf for all other outputs unless otherwise speci?d. symbol parameter 12 mhz clock variable clock unit min. max. min. max. external program memory; see fig.55 1/f clk system clock frequency; see note 1 3.5 12 mhz t lhll ale pulse width 58 ? t clk ? 25 ? ns t avll address valid to ale low 17 ? 0.5 t clk ? 25 ? ns t llax address hold after ale low 17 ? 0.5 t clk ? 25 ? ns t lliv ale low to valid instruction in ? 102 ? 2 t clk ? 65 ns t llpl ale low to psen low 17 ? 0.5 t clk ? 25 ? ns t plph psen pulse width 80 ? 1.5 t clk ? 45 ? ns t pliv psen low to valid instruction in ? 65 ? 1.5 t clk ? 60 ns t pxix input instruction hold after psen 0 ? 0 ? ns t pxiz input instruction ?at after psen ? 17 ? 0.5 t clk ? 25 ns t aviv address to valid instruction in ? 128 ? 2.5 t clk ? 80 ns t plaz psen low to address ?at ? 10 ? 10 ns external data memory; see fig.56 and fig.57 t rlrh rd pulse width 150 ? 3 t clk ? 100 ? ns t wlwh wr pulse width 150 ? 3 t clk ? 100 ? ns t rldv rd low to valid data in ? 118 ? 2.5 t clk ? 90 ns t rhdx data hold after rd 0 ? 0 ? ns t rhdz data ?at after rd ? 63 ? t clk ? 20 ns t lldv ale low to valid data in ? 183 ? 4 t clk ? 150 ns t avdv address to valid data in ? 210 ? 4.5 t clk ? 165 ns t llwl ale low to rd or wr low 75 175 1.5 t clk ? 50 1.5 t clk +50 ns t avwl address valid to rd or wr low 92 ? 2t clk ? 75 ? ns t qvwx data valid to wr transition 12 ? 0.5 t clk ? 30 ? ns t whqx data hold after wr 6 ? 0.5 t clk ? 25 ? ns t qvwh data valid time wr high 162 ? 3.5 t clk ? 130 ? ns t rlaz rd low to address ?at ? 0 ? 0ns t whlh rd or wr high to ale high 17 67 0.5 t clk ? 25 0.5 t clk +25 ns external clock; see fig.58 t chcx high time 37.5 45.8 t clk 0.45 t clk 0.55 ns t clcx low time 37.5 45.8 t clk 0.45 t clk 0.55 ns t clch rise time ? 20 ? 20 ns t chcl fall time ? 20 ? 20 ns
2000 jul 26 147 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 note 1. parts a guaranteed to operate down to 0 hz. table 112 i 2 c-bus interface timing all values referred to v ih(min) and v il(max) levels; see fig.61. notes 1. at 100 kbit/s. at other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 s. 3. spikes on the sda and scl lines with a duration of less than 3 t clk will be filtered out. maximum capacitance on bus-lines sda and scl = 400 pf. 4. t clk = 1/f clk = one oscillator clock period at pin xtal1. for 83 ns < t clk < 285 ns (12 mhz > f clk > 3.5 mhz) the si01 interface meets the i 2 c-bus specification for bit-rates up to 100 kbit/s. 5. these values are guaranteed but not 100% production tested. uart timing - shift register mode; see fig.59 t xlxl serial port clock cycle time 500 ? 6 t clk ? ns t qvxh output data setup to clock rising edge 284 ? 5 t clk ? 133 ? ns t xhqx output data hold after clock rising edge 53 ? t clk ? 30 ? ns t xhdx input data hold after clock rising edge 0 ? 0 ? ns t xhdv clock rising edge to input data valid ? 284 ? 5 t clk ? 133 ns symbol parameter i 2 c-bus input output t hd;sta start condition hold time 7t clk > 4.0 s (1) t low low period of the scl clock 8t clk > 4.7 s (1) t high high period of the scl clock 7t clk > 4.0 s (1) t rc rise time of scl signals 1 s ? (2) t fc fall time of scl signals 0.3 s < 3.0 s (3) t su;dat1 data set-up time 250 ns > 10 t clk ? t rd t su;dat2 sda set-up time (before repeated start condition) 250 ns > 1 s (1) t su;dat3 sda set-up time (before stop condition) 250 ns > 4 t clk t hd;dat data hold time 0 ns > 4 t clk ? t fc t su;sta set-up time for a repeated start condition 7t clk > 4.7 s (1) t su;sto set-up time for stop condition 7t clk > 4.0 s (1) t buf bus free time between 7t clk > 4.7 s (1) t rd rise time of sda signals 1 s ? (2) t fd fall time of sda signals 0.3 s < 0.3 s (3) symbol parameter 12 mhz clock variable clock unit min. max. min. max.
2000 jul 26 148 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.55 external program memory read cycle. handbook, full pagewidth mbc483 - 1 t lhll t avll t llpl t plph t lliv t pliv t llax t plaz t pxix t pxiz instr in a0 - a7 a0 - a7 a8 - a15 a8 - a15 ale psen port 0 port 2 t aviv
2000 jul 26 149 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 handbook, full pagewidth mbc485 - 1 ale psen port 0 port 2 rd t avwl t avll t llax t llwl t rlrh rhdx t t whlh a0 - a7 from ri or dpl data in a0 - a7 from pcl instr in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph rhdz t t avdv rldv t t lldv fig.56 external data memory read cycle.
2000 jul 26 150 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 andbook, full pagewidth mbc486 - 1 ale psen port 0 port 2 wr t avwl t avll t llax qvwx t t llwl t wlwh whqx t t whlh a0 - a7 from ri or dpl data out a0 - a7 from pcl instr in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph t qvwh fig.57 external data memory write cycle.
2000 jul 26 151 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.58 external clock drive xtal1. handbook, full pagewidth mga175 t high t low t clk t f v ih1 v ih1 0.8 v 0.8 v v ih1 v ih1 0.8 v 0.8 v t r fig.59 shift register mode timing waveforms. handbook, full pagewidth mbc475 instruction ale clock 8 7 6 5 4 3 2 1 0 valid write to sbuf output data clear ri input data t xlxl t xhqx t qvxh t xhdv t xhdx set ri set ti valid valid valid valid valid valid valid
2000 jul 26 152 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.60 ac testing input, output waveform (a) and float waveform (b). ac testing inputs are driven at 2.4 v for a high and 0.45 v for a low. timing measurements are taken at 2.0 v for a high and 0.8 v for a low, see fig.60 (a). the float state is defined as the point at which a port 0 pin sinks 3.2 ma or sources 400 a at the voltage test levels, see fig.60 (b). handbook, full pagewidth mga174 2.0 v 0.8 v 2.4 v 0.45 v 2.0 v 0.8 v 2.4 v 0.45 v float (b) (a) 2.4 v 0.45 v 2.0 v 0.8 v test points
2000 jul 26 153 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 handbook, full pagewidth t rd t fd t rc t fc t hd;sta t low t high t su;dat1 t hd;dat t su;dat2 t su;dat3 0.7 v dd 0.3 v dd t su;sto t buf t su;sta sda (input / output) scl (input / output) start condition repeated start condition stop condition start or repeated start condition 0.7 v dd 0.3 v dd mbc482 fig.61 i 2 c interface timing.
2000 jul 26 154 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.62 i dd as a function of frequency. i dd (ma) 50 40 30 20 10 3 6 9 12 (mhz) frequency at xtal1 maximum active i dd fig.63 i dd test conditions, active mode. all other pins are disconnected. (1) the following pins must be forced to v dd : ea and port 0. (2) the following pins must be forced to v ss : av ss and rst. (3) port 1.6 and 1.7 should be connected to v dd through resistors of sufficiently high value such that the sink current into these pins cannot exceed the i ol1 spec of the pins. (4) the following pins must be disconnected: xtal2 and all pins not specified above. (5) note, during reset = active the power consumption will be reduced by an internal clock divider by two. handbook, full pagewidth mhi056 p1.6 p1.7 rst xtal2 P8XC591 xtal1 v ss v dd i dd v dd av ss v dd ea p0 (n.c.) clock signal v dd
2000 jul 26 155 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.64 i dd test condition, idle mode. all other pins are disconnected. (1) the following pins must be forced to v dd : port 0 and rst. (2) the following pins must be forced to v ss : av ss and ea. (3) port 1.6 and 1.7 should be connected to v dd through resistors of sufficiently high value such that the sink current into these pins cannot exceed the i ol1 spec of the pins. these pins must not have logic 0 written to them prior to this measurement. (4) the following pins must be disconnected: xtal2 and all pins not specified above. handbook, full pagewidth mhi057 p1.6 p1.7 rst xtal2 P8XC591 xtal1 v ss v dd i dd v dd av ss v dd ea p0 (n.c.) clock signal v dd fig.65 clock signal waveform for i dd tests in active and idle modes t clch = t chcl = 10 ns. handbook, full pagewidth 0.7 v dd 0.2 v dd ? 0.1 v dd ? 0.5 0.5 v t chcl t chcl mhi058 t clcx t clk t chcx
2000 jul 26 156 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 fig.66 i dd test condition, power-down mode. all other pins are disconnected. v dd = 2 v to 5.5 v (1) the following pins must be forced to v dd : port 0 and rst. (2) the following pins must be forced to v ss : av ss and ea. (3) port 1.6 and 1.7 should be connected to v dd through resistors of sufficiently high value such that the sink current into these pins cannot exceed the i ol1 spec of the pins. these pins must not have logic 0 written to them prior to this measurement. (4) the following pins must be disconnected: xtal2 and all pins not specified above. handbook, full pagewidth mhi057 p1.6 p1.7 rst xtal2 P8XC591 xtal1 v ss v dd i dd v dd av ss v dd ea p0 (n.c.) clock signal v dd
2000 jul 26 157 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 25.1 timing symbol de?itions oscillator: f clk = clock frequency t clk = clock period timing symbols (acronyms): each timing symbol has five characters. the first character is always a 't' (= time). the remaining four characters of the symbol (typed in subscript), depending on their relative positions, indicate the name of a signal or the logical status of that signal. the designations are as follows: a =address c = clock d = input data h = logic level high i = instruction (program memory contents) l = logic level low or ale p = psen q = output data r = rd signal t = time v = valid w = wr signal x = no longer a valid logic level z = float examples: t avll = time for address valid to ale low t llpl = time for ale low to psen low 26 eprom characteristics the P8XC591 contains three signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an P8XC591 manufactured by philips: ? (030h) = 15h indicates manufactured by philips ? (0031h) = 98h indicates hamburg ? (60h) = 01h indicates p87c591 26.1 program veri?ation if security bits 2 or 3 have not been programmed, the on-chip program memory can be read out for program verification. if the encryption table has been programmed, the data presented at port 0 will be exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. 26.2 security bits with none of the security bits programmed the code in the program memory can be verified. if the encryption table is programmed, the code will be encrypted when verified. when only security bit 1 (see table 113) is programmed, movc instructions executed from external program memory are disabled from fetching code bytes from the internal memory. ea is latched on reset and all further programming of the eprom is disabled. when security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. when all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. table 113 program security bits for eprom devices p = programmed; u = unprogrammed. note 1. any other combination of the security bits is not defined. program lock bits (1) sb1 sb2 sb3 protection description 1 u u u no program security features enabled. (code verify will still be encrypted by the encryption array if programmed.). 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 p p u same as 2, also verify is disabled. 4 p p p same as 3, and external memory execution is disabled.
2000 jul 26 158 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 27 package outlines unit a a min. max. max. max. max. 1 a 4 b p e (1) (1) (1) eh e z y w v references outline version european projection issue date iec jedec eiaj mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 0.51 2.16 45 o 0.18 0.10 0.18 dimensions (millimetre dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.01 inches maximum per side are not included. sot187-2 d (1) 16.66 16.51 h d 17.65 17.40 e z 2.16 d b 1 0.81 0.66 k 1.22 1.07 k 1 0.180 0.165 0.020 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.020 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e e e d 16.00 14.99 0.630 0.590 16.00 14.99 0.630 0.590 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 k 1 k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 mo-047ac 0 5 10 mm scale 95-02-25 97-12-16 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e
2000 jul 26 159 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 0.85 0.75 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 92-11-17 95-02-04 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y a 1 a l p q detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
2000 jul 26 160 philips semiconductors preliminary speci?ation single-chip 8-bit microcontroller with can controller P8XC591 28 soldering 28.1 plastic leaded-chip carriers/quad ?t-packs 28.1.1 b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. 28.1.2 b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. 28.1.3 r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages. for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. 29 definitions 30 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?ation this data sheet contains target or goal speci?ations for product development. preliminary speci?ation this data sheet contains preliminary data; supplementary data may be published later. product speci?ation this data sheet contains ?al product speci?ations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this speci?ation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?ation.

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